fpga led

tle转换为六根数的c++源代码，英文原版代码，测试可用(tle converted to six the number of c++ source code, the English original code, test available)

作为一种古老的接口，支持的分辨率远高于HDMI和DVI，1920分辨率根本不在话下，本设计在QUARTUS下设计，编译，加载运行通过效果良好。

说明：  DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog(DA-chip SPI protocol output control does not read write-only FPGA with verilog)

通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)

本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)

使用verliog实现ps2键盘接口的驱动，通过altera cyclone 第四代验证通过(Use verliog implement ps2 keyboard interface driven by a fourth-generation verified by altera cyclone)

利用康芯公司的FPGA芯片设计制作频率计，实现对频率的测量。(Kang core using FPGA chip design company frequency meter, realize the frequency measurements.)

说明：  滤波器就是对特定的频率或者特定频率以外的频率进行消除的电路，被广泛用于通信系统和信号处理系统中。(Filter is a circuit that eliminates specific frequencies or frequencies other than specific frequencies. It is widely used in communication systems and signal processing systems.)

这是针对采用赛灵思 AXI VDMA 的数据表。它涵盖 Xilinx AXI VDMA，框图的设计。AXI VDMA 的功能是以流式传输的视频数据，从外部存储器。

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)