axi slave

can总线通信参考资料，实现can总线通信传输

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)

ALTERA FPGA CLPD

CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。(The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

开关电源中用单片机产生可调电压控制PWM波程序,ADC0832读取输出电压(Single-chip switching power supply using adjustable voltage control PWM wave generation process, ADC0832 read the output voltage)

说明：  一篇关于LDPC解码算法的FPGA用VHDL实现的PDF文件，老外写的，还可以，可以参考，欢迎大家下载！(A PDF about the FPGA implementation of LDPC algorithm, written by foreigners, but also, you can refer to, welcome to download!)

DDR3 控制器，axi4_full 模式， burst长度为16，应用于xilinx平台。(DDR3 interface controller， axi4_full working mode with burst length 16, can operate on the xilinx platform.)

说明：  文档科斯塔斯环路滤波器。。。。。般若撒根本(wendangsafwrfgvearbeabf)