fft，ifft verilog代码

用Verilog实现的脉冲宽度调制程序，在quartus平台上测试成功。(Using Verilog implementation of pulse width modulation, in quartus platform test successfully.)

PRBS的验证就是PRBS的产生的反过程，具体方法是Transceiver接收端首先将收到的数据寄存一拍（并行 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存(Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache)

VHDL code for converting BCD to Decimal

使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )

完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)

基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

基于DSP28335的产生ADc采样的程序(Program for generating ADC sampling based on DSP28335)