多层次的中国

说明：  俄罗斯方块游戏，采用Verilog编写，整个工程文件，TFT/VGA显示(Tetris game, written by Verilog, the whole project file, TFT / VGA display)

it shows bcd counter

OQPSK在AWGN和频率选择性衰落信道中的仿真(OQPSK the AWGN and frequency selective fading channel simulation)

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

说明：  基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)

verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用(verilog code for serial port transmit and receive code, with source code and test files, and accurate available)

基于VHDL语言的CORDIC算法实现，用于计算sin(x),cos(x)等，实测可用(Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available)

基于VHDL语言的七段显示管程序， 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)

ARM7 VERILOG源码，非常精简，3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)

说明：  文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)