四位密码锁

很有用的ＳＤＲＡＭ读写代码，上板验证有效

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

说明：  自己写的CRC的Verilog代码，在网上收集的crc相关的代码以及crc的matlab仿真代码(The CRC Verilog code written by myself, CRC related codes collected on the Internet and CRC matlab simulation code)

基于VHDL的TPC译码器的设计，简述了tpc译码的算法步骤，tpc硬件实现的模块和部分vhdl程序(TPC decoder VHDL-based design, outlines the decoding algorithm steps tpc, tpc hardware modules and some vhdl program)

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

CSC RGB2YUV Verilog source code

verilog 模糊PID 通过修改MIF文件 可以完成单个参数整定(FUZZY pid by verilog HDL)

这是一个nios工程，控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的，MCU软核程序有C语言编写。通过这一个完成的工程，你就会明白SOPC的一些实现方法。(This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization. )