Verilog prepared using USB download cable program realize USB protocol and JTAG...

FPGA设计频率计全套资料，我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful

Generating a wider ALU from two small ones

ADC Reference code!Clock 100kHz

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

VHDL与源代码包-and VHDL source code

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

基于FPGA的键盘程序代码，可用单片机控制-FPGA-based keyboard program code can be used SCM control

说明：  fpga设计常用资料大全，包含常用的FPGA程序资料，对FPGA学习者有很大的帮助。(Encyclopedia of common information fpga design, FPGA that contains commonly used procedures for information on the FPGA is very useful to learners.)

用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU

电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.