Verilog prepared using USB download cable program realize USB protocol and JTAG...

uart接收模块 // 波特率：9600 // 数据位：8 // 停止位：1 // 校验位：0(UART receive module Baud rate: 9600 / / / data: 8 / / stop: 1 / / check digit: 0)

verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

说明：  一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)

VHDL经典设计，值得参考。压缩包里面文件直接用记事本打开即可。-VHDL design classic, it is also useful.

这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source

用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration

rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)

FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)

VHDL开发环境，电梯控制系统，实现电梯的上下传送控制。-VHDL development environment, elevator control system, transmission control up and down elevators.