cache 闪存 快速缓存

一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)

Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage

This programa execute calc of CRC by use a table.

misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

说明：  基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)

FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)

VHDL Bible. It is a must read for any front end vlsi designer.

说明：  通过iic总线实现数据的读和写，以及基于的modelsim测试。(Through the iic bus to achieve data reading and writing,and based on the modelsim test.)

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)