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qianzhaowang
说明: 一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP,实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分:1
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3Code_for_Medx
3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。
(3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.)
- 2012-07-30 00:49:45下载
- 积分:1
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wirebus总线nand flash controller
wirebus总线nand flash controller,基础入门控制器,内存管理,fpga实现。已编译通过。编译平台quartus ii
- 2023-02-28 07:40:03下载
- 积分:1
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3he11
产生SH,SP,RS,SP,φ1,φ2驱动脉冲,用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)
- 2013-05-15 20:50:30下载
- 积分:1
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锁相环Verilog代码
锁相环是通信领域最基本的元件,同时在FPGA上也有广泛的应用,本代码是锁相环PLL的Verilog HDL代码,简单易读,能够实现PLL基本的锁相、分频等功能
- 2022-01-26 00:06:30下载
- 积分:1
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Booth算法的Verilog
模块
- 2022-05-09 04:12:07下载
- 积分:1
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DSP28335_SPI_FPGA_RECE
DSP28335与FPGA通过spi通信,此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)
- 2020-12-09 13:39:19下载
- 积分:1
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pinlvji
频率计
测量范围1-100MHz
测量阈值0.1s
计数部分为FPGA/CPLD
语言VHDL
显示部分为51
单片机加八位数码管
语言C(Frequency meter
Measuring range 1-100 MHZ
Measure threshold is 0.1 s
Count part of FPGA/CPLD
Language VHDL
Display part of 51
MCU with eight digital tube
Language C)
- 2020-10-30 20:39:55下载
- 积分:1
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Y312448.zip
基于VHDL的SDH专用芯片的TOP-DOWN设计,
内有全套源码以及图片,内容详尽,绝对真实可靠!(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)
- 2008-05-12 19:21:03下载
- 积分:1
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异步FIFO代码
异步fifo设计代码,包含完整过程,需要的朋友可以参考,实际设计代码,参考了多个版本,通过了项目验证,已经实际应用。
- 2022-02-24 12:15:30下载
- 积分:1