原创verilog_16bit_risc_cpu，带相关PPT和testbench

FPGA 全数字化实现信号发生器，产生正弦、三角、方波；幅值频率可调

1、PC和寄存器组使用时钟触发。 2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。 3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。 4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked. 2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit. 3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own. 4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)

说明：  Basic principle of LDPC code and FPGA implementation of LDPC code

关于FPGA的一些例程，包括CORDIC数字计算机的设计，RS(204,188)译码器的设计等。(Some routines on FPGA include the design of CORDIC digital computers, the design of RS (204188) decoders, etc.)

在PVI接收16位并行数字流（视频），其次是一个时钟信号（英尺= 29兆赫），小写字母

spartan3e 开发板上调试ARM7功能，添加了基本的IO与UART，代码包括逻辑部分与Keil C测试工程

DE2-115 + D5M Camera to VGA PC

Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol

自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)

基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)