与寄存器 8 位规模 comparater

This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.

这里是verilog代码 ；8bit  ；吠陀乘数还可以使用这个模块的设计…你想要更大的…

驱动0.96寸的oled显示数字和字母，(Drive 0.96 inch OLED to display numbers and letters.)

AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23)

雷达基本恒虚警处理，CA-CFAR(单元平均恒虚警处理),OS-CFAR（有序类恒虚警处理）,SO-CFAR（选小类恒虚警处理），(radar basic constant alarm operation,obtaining os-cfar,so-cfar,os-cfar,ca-cfar)

对delta sigma进行设计，实现delta sigma ADC的设计(this is use for delta sigma adc ,and design and achieve adc)

交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现(VHDL core)

华为FPGA设计全套资料，学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)

握手程序，可以完美实现跨时钟域的数据传输(handshake and testbench，verilog HDL)

/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息. // 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测. // 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电 // 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)