6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成

一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)

This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.

说明：  fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

说明：  基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。(FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.)

用verilog实现的一个2抽头RLS自适应滤波器的代码(A realization with verilog HDL code of a two-tap RLS adaprive fliter )

文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术，研制和 设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and Design of high resolution, high stability function of the signal )

七人表决器，当有四人或四人以上的人同意是，表决通过。每个裁判控制一个开关，高电平表同意，在quartusII上用全加器来实现，当表决通过时，实验箱上的LED灯亮

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

能够成功的实现走马灯功能，使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz