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DDR-SDRAM-Controller
DDR SDRAM控制器verilog代码及中文说明文档(DDR SDRAM Controller Using Virtex-5 FPGA Devices)
- 2016-01-20 13:58:46下载
- 积分:1
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FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
FPGA实现的LCD接口,VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
- 2022-09-14 14:30:09下载
- 积分:1
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UART模块用VHDL。
用VHDL语言编写的串口通讯模块,可以实现发送和接受功能。-A UART module writen in VHDL.
- 2022-12-24 06:35:03下载
- 积分:1
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E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
- 2023-06-23 08:30:04下载
- 积分:1
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water_light
Verilog语言的流水灯设计程序,对初学者很有用。(Water lights Verilog language design program useful for beginners.)
- 2015-03-15 13:48:43下载
- 积分:1
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Signed-Arithmetic-in-Verilog-2001
有符号数的完整讲义和例子Verilog 2001(Signed Arithmetic in Verilog 2001, paper with examples)
- 2011-01-18 17:15:09下载
- 积分:1
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oc i2c master
NIOSII I2C接口模块及驱动程序,并含有测试程序。对想开发NIOS的工程师很有帮助(NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful)
- 2007-08-20 19:37:02下载
- 积分:1
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DisplayPort Link training optimization
说明: 介绍了Displayport规格中lind training的背景研究,设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining
the signal integrity becomes increasingly more difficult. For many of todays
commonly used video interfaces, there are devices that can be used to assist in this
matter. However, the use of such a device is only partially documented in the DisplayPort
specification for the receiving image device, which means that the receiving
side of the video link is free to choose its own implementation. This report presents,
together with background research and design decisions, a suggestion for such an
implementation. This implementation would need to be compatible towards a wide
range of possible video Source devices and DisplayPort cables.)
- 2021-01-11 16:48:49下载
- 积分:1
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用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-25 16:18:57下载
- 积分:1
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一种学习用的小程序,主要用与VHDL仿真的全加器的一段代码!大家可以下载进行修改于仿写...
一种学习用的小程序,主要用与VHDL仿真的全加器的一段代码!大家可以下载进行修改于仿写-A learning to use a small program, mainly used with the VHDL simulation of a full-adder code! You can download the modified Yu Fang Xie
- 2022-01-25 21:36:29下载
- 积分:1