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说明: 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA,包
括:步骤一、计算重构矩阵;步骤二、重构方位向
多通道数据,包括:步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零,并进行方位向傅里
叶变换;步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘,得到重构完成的方位向数据;(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分:1
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fpga
verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)
- 2017-07-27 20:05:25下载
- 积分:1
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rotary
Spartan 3E上的Rotary encoder控制程序,及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)
- 2010-11-27 01:40:13下载
- 积分:1
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assign LEDs to Siwitches on altera fpga
此代码描述如何通过使用董事会。这个谋杀案是为altera董事会写的。
- 2022-09-16 16:45:03下载
- 积分:1
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test-bench
如何编写测试文件,,test bench的编写方法和是列,,总结的非常好的东西(how to code test bench in verilog)
- 2012-03-31 08:38:24下载
- 积分:1
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SMBUS总线的verilog实现
实现两个状态机和不同的数据传输方式,按照smbus总线的要求进行调节每位的传输,从起始位到终值位,能够较好的实现
- 2022-03-25 14:06:09下载
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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出,介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分:1
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or2a
使用vhdl语言设计一位全加器,在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分:1
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sumador 4 位空格 de 2 numeros hexadecimales con resultado en 十进制 en 联合国显示德 7 segmentos 语言
电路建模在总和 2 的 4 位十六进制的数字,将结果转换为十进制数和显示上 7 分割数据的语言。
- 2022-03-03 02:22:21下载
- 积分:1
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基于FPGA的多路同步脉冲发生器设计1
说明: 采用FPGA(现场可编程门序列)编写VHDL语言设计多路同步脉冲发生器,对信号进行分频处理,实现四路信号相位相差T/16和T/8的延迟相位输出,实现的四路脉冲与传统的脉冲同步器不同,它具有高集成度,高通用性,容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and T / 8 delay phase output, the realization of the four-way pulse is different from the traditional pulse synchronizer, it has the characteristics of high integration, high-throughput, easy adjustment and high reliability.)
- 2020-03-18 20:52:05下载
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