VHDL language H.264 realize the opencore, meaning that documents, information su...

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)

基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)

verilog实现的LMS的算法，另外有tb文件可以测试已测试代码正确……(verilog implementation of LMS algorithm, another tb files can test the code has been tested properly ......)

它是一个基于verilog的数字时钟，显示时-分-秒，它可以手动输入，并为时、分和秒分配3个开关第二，它数字时钟频率是实时设置的。我自己用逻辑开发的。。。

vhdl参考程序，供初学者参考使用-VHDL reference procedures, their use and reference for beginners

篮球24s计时器，元器件简单，功能复杂。满足小型计时需要。

基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)

在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)

说明：  there's a clock divider for DE2 altra board clock (50MHz)

一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter