VHDL language H.264 realize the opencore, meaning that documents, information su...

FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL

可以实现对任意波形分任意频，分频加减通过按键实现。-Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.

dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

说明：  华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码，使初学者能够迅速熟悉基本的HDL 建模；同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)

用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,

飞思卡尔智能车芯片模块程序 MC9S12XS128 测试通过(freescale smart car for MC9S12XS128)

在matlab仿真的基础上，用maxplus2实现等波纹法的程序代码(In matlab simulation, based on the use of such corrugated maxplus2 realize law code)