自动控制原理(胡寿松第四版)及答案

介绍了灰色预测方法以及Matlab实现该算法的具体步骤，（由于有些质料是在网上下载的，有些质料是网页版的 或者直接看附带的10.ppt）；进行了大量的实验 效果好！得出的结果进行关联度分析和后验差检验！并对模型进行评价！

MIMO OFDM Simulator:OFDM.m: OFDM Simulator (outer function) create_channel.m: Generates a Rayleigh fading frequency-selective channel, parametrized by the antenna configuration, the OFDM configuration, and the power-delay profile. svd_decompose_channel.m: Since full channel knowledge is assu

刚整理的visio形状库，太多了分四个压缩包上传，这是第一辑，以小图形为主，你想要的应该都能有

Hyres 3.1(分辨率测试软件) 和ISO12233测试标板的使用和判读，有兴趣的童鞋可以看看。

【实例简介】多传感器数据融合在数据融合领域是一个不错的

利用matlab添加wav音频文件，并在文件上添加用randn产生均值为0方差为1的正态分布白噪声，再用IIR、FIR滤波器滤波。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

操作系统课程设计报告-多用户文件系统的模拟，本报告中的文件系统是多用户多级目录的文件系统。实验中定义用户的上限为5个，目录结构采用多级目录结构。资源内含详细的文档说明和源代码

5新概念模拟电路-源电路（信号源和电源）（Analog-Circuit-V）pdf

C语言版本的DES加密解密算法,代码!(DEV C++编译通过)纯粹C语言写的,我在DEV C++上编译运行过.最近一个多星期搞加密解密发现网上版本忒多,但C的少而且不全,所以现在想到贡献出来,希望给大家帮助!