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示波器设计源工程

于 2021-01-02 发布
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下载积分: 1 下载次数: 1

代码说明:

说明:  示波器设计,首先,AD模块对模拟信号进行采样,触发电路根据采样信号判断触发条件。满足触发条件后,连续采样一定数量的点(本系统中为640个点),存储到RAM中。峰峰值、频率计算模块对RAM中储存的波形数据进行计算,得到波形的频率以及峰峰值;VGA模块将波形显示出来,并显示计算得到的峰峰值和频率数值。(Firstly, the ad module samples the analog signal, and the trigger circuit judges the trigger condition according to the sampling signal. After meeting the trigger conditions, a certain number of points (640 points in this system) are sampled continuously and stored in RAM. The peak to peak and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak to peak of the waveform; the VGA module displays the waveform and displays the calculated peak to peak and frequency values.)

文件列表:

示波器设计源工程\lab4, 0 , 2021-01-01
示波器设计源工程\lab4\readme.txt, 1080 , 2021-01-01
示波器设计源工程\lab4\Src, 0 , 2021-01-01
示波器设计源工程\lab4\Src\Constraint, 0 , 2021-01-01
示波器设计源工程\lab4\Src\Constraint\oscilloscope.xdc, 1831 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\char_rom_mapping.v, 10156 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock.v, 4488 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock.veo, 4217 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock.xci, 84501 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock.xdc, 2711 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock.xml, 269484 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock_board.xdc, 60 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock_clk_wiz.v, 8268 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\clock_ooc.xdc, 2482 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\doc, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\doc\clk_wiz_v5_4_changelog.txt, 6415 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\mmcm_pll_drp_func_7s_mmcm.vh, 24240 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\mmcm_pll_drp_func_7s_pll.vh, 19041 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\mmcm_pll_drp_func_us_mmcm.vh, 24226 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\mmcm_pll_drp_func_us_pll.vh, 22052 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\mmcm_pll_drp_func_us_plus_mmcm.vh, 31888 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock\mmcm_pll_drp_func_us_plus_pll.vh, 19555 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\clock_control.v, 1874 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0.dcp, 4001 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0.veo, 3035 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0.xci, 3009 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0.xml, 18021 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0_funcsim.v, 6100 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0_funcsim.vhdl, 6587 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0_stub.v, 1234 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\debounce_0_stub.vhdl, 1288 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sim, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sim\debounce_0.v, 2713 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sim_1, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sim_1\new, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sim_1\new\debounce_tb.v, 898 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sources_1, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sources_1\new, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\sources_1\new\debounce.v, 1020 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\synth, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\debounce_0\synth\debounce_0.v, 2982 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\Fre_Calculate.v, 4796 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\Fre_Vopp_mapping_rom.v, 5245 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0.zip, 3007 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\component.xml, 9758 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sim_1, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sim_1\new, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sim_1\new\debounce_tb.v, 898 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sources_1, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sources_1\new, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\sources_1\new\debounce.v, 1020 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\xgui, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_debounce_1.0\xgui\debounce_v1_0.tcl, 205 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_vga_1.0.zip, 3414 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_vga_1.0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_vga_1.0\component.xml, 15615 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_vga_1.0\vga.v, 2004 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_vga_1.0\xgui, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_vga_1.0\xgui\vga_v1_0.tcl, 5928 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0.zip, 8895 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\component.xml, 29623 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\ip, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\ip\xadc_wiz_0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\ip\xadc_wiz_0\xadc_wiz_0.xci, 37291 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\new, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\new\xadc.v, 8720 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\xgui, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\IP_Catalog\XUP_xadc_1.0\xgui\xadc_v1_0.tcl, 13347 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\OSC_top.v, 5619 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\trigger.v, 875 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\sim, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\sim\vga_0.v, 3092 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\synth, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\synth\vga_0.v, 3394 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga.v, 2004 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0.dcp, 8059 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0.veo, 3263 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0.xci, 5350 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0.xml, 23136 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0_funcsim.v, 28704 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0_funcsim.vhdl, 35252 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0_stub.v, 1435 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_0\vga_0_stub.vhdl, 1488 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\vga_initials.v, 8795 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\waveform_mapping_rom.v, 36140 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\waveform_ram.v, 21964 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0\ip, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0\ip\xadc_wiz_0, 0 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0\ip\xadc_wiz_0\xadc_wiz_0.upgrade_log, 628 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0\ip\xadc_wiz_0\xadc_wiz_0.v, 9165 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0\ip\xadc_wiz_0\xadc_wiz_0.xci, 34439 , 2021-01-01
示波器设计源工程\lab4\Src\HDL_source\xadc_0\ip\xadc_wiz_0\xadc_wiz_0.xdc, 2484 , 2021-01-01

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