Matlab实现FCM算法

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MATLAB编程处理体表肌电信号，包括文件读取，滤波，画图显示时域、频域图。

里面有各种中值滤波去噪MATLAB程序，包含标准、开关、极值、自适应等中值滤波。

输入图像分割结果和标答，得到评价指标P,R，F。

ADI公司器件PCB封装FOOTPRINT,ADI公司器件PCB封装,AnalogDevices.zip,AltuimDesigner版本

一个国外开发者写的Matlab工具箱，主要用于优化无无约束的问题。

【实例简介】该文介绍基于Matlab/ Simulink 进行雷达系统仿真的基本规范,开发了有关的雷达系统仿真模型库,并在该平台上对某脉冲多普勒雷达系统进行了仿真,给出了仿真结果和分析。

论文，高速光纤通信与数字信号处理。相干光接收，频偏估计，相位估计，算法。Y175785独创性(或创新性)声明本人声明所呈交的论文是本人在导师指导下进行的研究工作及取得的研究成果。尽我所知,除了文中特别加以标注和致谢中所罗列的内容以外,论文中不包含其他人已经发表或撰写过的研究成果,也不包含为获得北京邮电大学或其他教育机构的学位或证书而使用过的材料。与我一同工作的同志对本研究所做的任何贡献均已在论文中作了明确的说明并表示了谢意。申请学位论文与套料若有不实之处,本人承担一切相关责任。本人签名:-/b日期:200列2关于论文使用授权的说明学位论文作者完全了解北京邮电大学有关保留和使用学位论文的规定,即:研究生在校攻读学位期间论文工作的知认产权单位属北京邮电大学学校有权保留并向国家有关部门或机构送交论文的复印件和磁盘,允许学位论文被查阅和借阅:学校可以公布学位论文的全部或部分内容,可以允许采用影印、缩印或其它复制手段保存、汇编学位论文。本人签名:日期:20°3.2导师签名:日期:100Gb/ s PM-QPSK相干光接收机载波频偏估计和相位恢复算法的研究摘要通信网络中高速率业务的不断发展,对现有的城域网络及省际、国际骨干通信网络的传输带宽提出了更高、更迫切的要求。从目前主流的1040Gbp光传输技术向100Gbs演进成为光传输技术的发展趋势。近年来大量研究表明,相位调制及相干接收是最具前景的100Gbs光传输方式。其中,采用相干接收技术的偏振复用QPSK( PM-QPSK传输系统最被业界认可。该系统的符号速率比比特率降低4倍,因此有较高的光谱利用率,且收发机结构相对简单实现相对容易。此外,信道中的各种损伤,如色散、载波频偏、相位偏移等导致的信号损伤,都能在接收机中通过电域的数字信号处理(DSP)来灵活地补偿。对调相信号,载波与本振间的频率和相位偏移会使信号产生较大的相位失真,频偏估计和相位恢复成为相干接收机中两个重要的功能模块。本文在国家863计划课题“1000b/s相干光传输关键技术研究(2009AA01Z221)”资助下,对上述系统接收机载波频偏和相位恢复算法展开了深入研究,主要内容如下:1.研究了 PM-QPSK的系统组成结构,重点研究了接收机DSP各组成模块的功能,并设计实现了相干接收机后端Maab仿真平台。2.详细分析了载波频偏估计算法,设计了算法并行处理实施方案以解决现有硬件处理速率不足够高的问题,并仿真验证了方案的可行性。设计了四次方频偏估计算法的并行结构;提出了基于误码性能反馈的 BA-PADE( BER-Aided pre-decision- based Angle DifferentialEstimator)算法,解决了传统PADE要求初始频偏设置与真实频偏接近的问题;提出了基于PADE的并行处理算法一一分组PADE( Grouped-PADE)。所设计方案均通过系统仿真验证了可行性。3.详细分析了载波相位恢复算法,为采用现有FPGA或DSP实现l00Gb/级信号处理,设计了载波相位恢复并行处理方案并仿真验证了方案的可行性。设计了基于Ⅴ iterbj- Viterbi的优化算法及其并行处理结构,将其同频偏估计并行算法联合进行了二进制定点仿真分析,仿真结果表明并行处理方案可显著降低硬件处理速率要求。关键词光传输相干接收频偏相位恢复THE RESEARCH OF FREQUENCY OFFSET ESTIMATIONAND PHASE RECOVERY ALGORITHMFOR 100Gbs OPTICAL COHERENT PM-QPSK RECEIVERABStRcTThe rapid development of high bit-rate services in communicationnetworks has instantly demanded a much higher bandwidth of coretransmission links in WAN, inter-province and international networks.The upgrade from the existing 10G/40G optical transmission to 100G hasbeen a trend. The research in recent years indicates that systems withphase modulation and coherent detection are the most promising, ofwhich PM-QPsk gets most recognitionThe PM-QPsK lowers the symbol rate as 1/4 of bit rate whichprovide high spectrum efficiency, and the transceiver structure ofPM-QPSK is simpler and so is easier to realize. Besides, with digitalalgorithms, the electrical Digital Signal Processing(DSP)in thee receivercan flexibly compensate the channel distortion caused by dispersion,carrier frequency offset and phase distortion. Since the phase distortioncaused by frequency and phase offset between lo and carrier is one ofthe main distortions in PM-QPSK, frequency offset compensation andphase recovery act as two of the core modules.With the support of National 863 Project"Research of the KeyTechnologies of 100Gb/s Optical Coherent Transmission Systems?", thisthesis mainly focuses on the research of the digital algorithms of carrierfrequency offset compensation and carrier phase recovery in the receiverof PM-QPSK system and the main contents are as follows1. Investigation of PM-QPSK structure, mainly on the receiver DSPstructure, including function of the several modules in this partDesigning and implementation of the Matlab simulation platform for theback-end of PM-QpsK receiver.2. Analysis on the carrier frequency offset estimation algorithmsdesigning of the parallel structure of the algorithms in order to break therestriction of hardware speed, with feasibility testified by simulationDesigning of the parallel structure of the 4 power method Designing ofBA-PADE (BER-Aided Pre-decision-based Angle Differential Estimator)based on BER feed-back to break the exact initialization restriction oftraditional PADE. Designing of a parallel operation scheme based onPADE, namely Grouped-PADE. Feasibility of both the forementionedscheme testified by simulation.3. Analysis on the carrier phase recovery algorithms, designing ofthe parallel operation scheme in order to realize phase recovery in100Gb/s PM-QPSK with current FPGA or DSP, with feasibility testifiedby simulation. Designing of the optimized and the parallel structure ofViterbi- Viterbi (V-V)method, and binary fixed-point simulation ofparallel v-v together with frequency offset algorithm, the result provedthat the scheme could observably lower the request to the hardwareoperation speedKEYWORDS optical transmission coherent detectionfrequency offset phase recovery

微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221

该程序是以色列科学家michael关于稀疏表示字典训练的一种算法仿真，并附有应用该字典进行图象去噪的实例.应用该程序可以按照readme中的提示 一步一步完成，先安装sparse-coding of large sets of signals文件夹中的内容,再安装ksvd程序就可以运行了.