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MicroElectronic Circuit Design

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微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221

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    imx274 datesheet,可以对接Hi3519V101,4K,分享一下SONYIMX274LQC-CAbsolute Maximum RatingsItemSymbolRatingsUnitSupply voltage(Analog)1ADD0.3to+3.3VSupply voltage(Digital 1)-0.5to+2.0Supply voltage(Digital 2)DDD20.5to+3.3VInput voltage(Digital)0.3toV。Dp+0.3VOutput voltage(Digital)-0.3toVD2+0.3Guaranteed operating temperature TOPR-30to+75°CStorage guarantee temperatureTSTG30to+80CPerformance guarantee temperature TsPEC10to+60Recommended Operating ConditionsItemSymbolRatingSupply voltage(Analog)VADD2.8±0.1Supply voltage(Digital 1)1.2±0.1VSupply voltage(Digital 2)1.8±0.1Input voltage(Digital)-0.1 to Vopp2+0.11 VADD: VDDSUB, VoDHCM, VoDHPX, VDDHDA, VDDHCP (2.8V power supplyVDDD1: VDDLCN, VDDLSC1 to 2, VDDLPA, VDDLPL1, VoDLPL2 to 3. VDDLIF (1.2V power supply)VDDD2: VDDMIO, VDDMIF (1.8V power supply)SONYIMX274LQC-CUSE RESTRICTION NOTICEThis USE RESTRIC TION NOTICE (Notice )is for customers who are considering or currently using theimage sensor products("Products")set forth in this specifications book. Sony Corporation Sony")mayat any time, modify this Notice which will be available to you in the latest specifications book for theProducts. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has itsown use restriction notice on the Products, such a use restriction notice will additionally apply betweerou and the subsidiary or distributor. You should consult a sales representative of the subsidiary ordistributor of sony on such a use restriction notice when you consider using the ProductsUse restrictionsThe Products are intended for incorporation into such general electronic equipment as office productscommunication products, measurement products, and home electronics products in accordance withthe terms and conditions set forth in this specifications book and otherwise notified by sony from timeYou should not use the Products for critical applications which may pose a life-or injury-threateningrisk or are highly likely to cause significant property damage in the event of failure of the products. Youshould consult your sales representative beforehand when you consider using the products for suchcritical applications. In addition, you should not use the products in weapon or military equipmentSony disclaims and does not assume any liability and damages arising out of misuse improper usemodification, use of the Products for the above-mentioned critical applications, weapon and militaryequipment, or any deviation from the requirements set forth in this specifications booklesign for SafetySony is making continuous efforts to further improve the quality and reliability of the products howeverfailure of a certain percentage of the products is inevitable. Therefore, you should take sufficient careto ensure the sate design of your products such as component redundancy, anti-contlagration featuresand features to prevent mIs-operation in order to avoid accidents resulting in injury or death fire orother social damage as a result of such failureExport ControlIf the Products are controlled items under the export control laws or regulations of various countriesapproval may be required for the export of the products under the said laws or regulationsYou should be responsible for compliance with the said laws or regulationsNo License Impliedo The technical information shown in this specifications book is for your reference purposes only. theavailability of this specifications book shall not be construed as giving any indication that sony and itscensors will license any intellectual property rights in such information by any implication or otherwiseSony will not assume responsibility for any problems in connection with your use of such information orfor any infringement of third-party rights due to the same. It is therefore your sole legal and financialresponsibility to resolve any such problems and infringementGoverning lawThis notice shall be governed by and construed in accordance with the laws of Japan, without referenceto principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relatingto this Notice shall be submitted to the exclusive jurisdiction of the Tokyo district Court in Japan as thecourt of first instanceOther Applicable Terms and ConditionsThe terms and conditions in the Sony additional specifications, which will be made available to you whenyou order the Products, shall also be applicable to your use of the Products as well as to thisspecifications book. You should review those terms and conditions when you consider purchasingand/or using the ProductsGeneral-0.0. 8SONYIMX274LQC-CContentsDescription---FeaturesDevice structureOptical Black Array and Readout Scan Direction---Absolute Maximum Ratings2233Recommended Operating Conditions---------------USE RESTRICTION NOTICEContentsOptical CePin Configuration------------------Pin description-------------------------458899hen using csl-2When using Sub-LVDS1210 Equivalent Circuit Diagram15Peripheral Circuit19System OutlineWhen using CSl-2When using Sub-LVDSElectrical Characteristics when using cs1-2--------------------------m---------------------------------21. DC Characteristics(CS1-2)a.8..4Current Consumption and Gain Variable Range(CSl-2Supply Voltage and l/O Voltage(CS1-2)2. AC Characteristics(CS1-222INCK, XCLR(CSl-2)22XHS, XVS(Output)(CSI-2)22IC Communication (CSI-2)23DMCKP/DMCKN, DMO(CSl-2Electrical Characteristics When Using Sub-LVDs-------------------m--------------------------1. DC Characteristics(Sub-LVDs)……Current Consumption and gain Variable Range sub-LVDS24Supply Voltage and l/o Voltage(Sub-LVDSLVDS Output DC Characteristics(Sub-LVDS2. AC Characteristics ( Sub-LVDS).........25INCK, XCLR, XVS(input), XHS (input)(Sub-LVDS25Serial Communication(Sub-LVDS)Sub-LVDS Output(Sub-LVDS)26Spectral Sensitivity Characteristics(CS1-2 and Sub-LVDS27Image Sensor Characteristics(CSl-2 and Sub-LVDS)-281. Zone Definition of Image Sensor Characteristics28mage Sensor Characteristics Measurement Method(CSl-2 and Sub-LVDS)1. Measurement conditions2. Color Coding of this Image Sensor and Readout..293. Definition of Standard Imaging Conditions29Setting Registers Using I"C Communication(When Using CSl-2Description of Setting Registers When Using I C communication31Pin Connection of Serial Communication Operation Specifications When Using I"C CommunicationRegister Communication Timing When Using I-C Communication12C Communication Protocol32Register Write and Read33Single Read from Random Location33Single read from current location; iidaiaii:;aaaa“Sequential Read Starting from Random LocationSequential Read Starting from Current Location34Single Write to Random Location35Sequential Write Starting from Random Location35Register Value Reflection Timing to Output Data(CSl-2)36SONYIMX274LQC-CSetting Registers Using Serial Communication (When Using Sub-LVDS)----------------37Setting Registers Using Serial Communication(Sub-LVDS).37Register Value Reflection Timing to Output Data( Sub-LVDS38Register Map…391. Description of Register2. Register Setting for Each Readout Drive Modeeadout Drive Modes( csl-2 and Sub-LVDS)---------------------551. Readout drive modes552. Relationship between Arithmetic Processing and the Number of Output bits in Each Readout Drive ModeImage Data Output Format When Using CSI-2--------------------------58Frame Format (CSI-2)58Frame Structure(CSl-258Embedded Data Line(CSl-2)59CSl-2 serial Output Setting(CSl-2)MIPI Transmitter(CSl-2)62Detailed Specification of Each Mode(CSl-2)---------------631. Horizontal/ Vertical Operation Period in Each Readout Drive Mode(CSl-22. Frame Rate Adjustment(CSl-23. Image Data Output Format CSl-265Vertical Arbitrary Cropping Function(CSl-2)-69Horizontal Arbitrary Cropping Function(CSl-272Electronic Shutter Timing When Using CSI-2------741. SHR, SVR, SMD Setting When Using CSl-2741-1. SHR, SVR Setting(CSl-2)741-2. Electronic Shutter Drive Mode(Csl-2)752. Integration Time in Each Readout Drive Mode and Mode Changes When Using CSl-2762-1. Integration Time in Each Readout Drive Mode(CSl-2762-2. Operation when Changing the Readout Drive Mode(CSl-2772-3. Low Power Consumption Drive in Integration Time When Using Roll ing Shutter Operation(CSl-2)78Image Data Output Format When Using Sub-LVDS--791. Sync Signals and Data Output Timing(Sub-LVDS)““792. Output Range of LVDS Output Data(Sub-LVDS)Detailed Specification of Each Mode(Sub-LVDS)删mHorizontal/Vertical Operation Period in Each Readout Drive Mode(sub-LVDs)..........2. Frame Rate Adjus咖ment(Sub-LVDS)……3. Image Data Output Format ( Sub-LVDS)Vertical Arbitrary Cropping(Sub-LVDS)Horizontal arbitrary cropping function(Sub-LVDS)----m94Electronic Shutter Timing When Using Sub-LVDS961. SHR, SVR Setting(Sub-LVDS)...962. SVR Operation (Sub-LVDS3. Electronic Shutter Drive Mode( Sub-LVDS)974. Integration Time in Each Readout Drive Mode and mode changes When Using Sub-LVDS984-1. Integration Time in Each Readout Drive Mode(Sub-LVDS984-2. Operation when Changing the Readout Drive Mode(Sub-LVDS994-3. Recommended Global Reset Shutter Operation Sequence(Sub-LVDS)1004-4. Interruptive Mode Change(Sub-LVDS4-5. Low Power Consumption Drive in Exposure Time (Sub-LVDS)…102Power-on/off Sequence when using CSI-2---1031. Power-on Sequence(CS2)……1032. Slew Rate Limitation of Power-on Sequence( CSI-21033. Power-off Sequence(CSl-2104Standby cancel sequence when using csl-2--------------------------105Power-on/off Sequence when using Sub-LVDS1161. Power-on Sequence(Sub-LVDS)1062. Slew Rate Limitation of Power-on Sequence(Sub-LVDS).........1063. Power-off Sequence(Sub-LVDS)107Standby Cancel Sequence(Sub-LVDs)------------108SONYIMX274LQC-CSpot Pixel specifications--109Spot Pixel Zone Definition109Notice on White Pixels SpecificationsMeasurement Method for Spot Pixels1111. Black or white pixels at high light1112. White pixels in the dark.3. Black pixels at signal saturated111Spot Pixel Pattern Specifications----------------m---------------------------------------------------112Stain Specifications---113Stain Zone definition113Stain Measurement method.113Relation between Image height and target Cra-----Marking---------mm---------------115Notes on Handling116Package outline ---118List of Trademark Logos and Definition Statements-------------119SONYIMX274LQC-COptical Center(Top View)Package outline10.70±0.1mmPKG lpinM1A1Optical centerM1010See page TBD Package Outl ine" for detailsOptical CenterPin ConfigurationBottom View)lpin index6666δ画δ尚画○●Bottom viewQ§③¤¤意○○○○○○○○10○o⑦A b CE F GMPin configurationSONYIMX274LQC-CPin DescriptionWhen using CS1-2Pin descriptionState inSymbolOADRemarks(CS|-2Standby modeLeave openA2TEST4ATest(No connectionA3VDDHDa Power a Analog power supply (2.8V)A4VDD SUB PowerAnalog power supply(2.8VA5VDDLSC1PowerD Digital power supply(1.2v)A6VssLSC1GNDDDigital GND(1.2V)A7VDDLPL3 Power D Digital power supply (1.2 V)A8VDDLIFowerDigital power supply(1.2v)Leave openB1TEST5ATest(No connectionB2ssHDA GND A Analog GND (2.8V)B3BIASRESResister connectionB4/BGRCapacitor connectionB5GNDD Digital GND (1B6XCLRReset pulse inputB7VssLPL3GNDDigital GND (1.2VB8 VsSLIF1 GND D Digital GND (1.2V)B9DMO4NDigital MiPl outputLow LevelData lane 4connectionB10DMO4P。DDigital MIPl outputLow LevelData lane 4connectionC1TESt3TestLeave open(No connectionC2XCECannect to 1.8 V power supplyLeave openC3TEST1D(No connectionC4TEST2estLeave open(No connectionC5VDDLPAPowerDDigital power supply(1.2v)C6 VDDLPL2 Power D Digital power supply (1.2V)C7 VssLPL2 GND D Digital GND(1.2V)c9DMO2NDigital MIPl outputLow LevelData lane 2connectionData lane 2C10DMO2PDigital MIPl outputLow LevelconnectionD1XHSDDDDHorizontal sync signal outputIf unused xHsleave openD2SDOlest outputLow Leve/ Leave openNo connectionVertical sync signal outpuf unusedⅩVSDleave openD9DMCKND Digital MIPl outputLow LevelClock laneconnectionD10DMCKPDigital MIPl outputLow levelClock LaneconnectionE1SCLDDDc communication clock inputC communication dataE2SDAOinput/outputSONYIMX274LQC-CPinPin descriptionSymbolADState inRemarksNoCS-2Stand by modeE3VSSLCBGNDDigital GND(1.2 V)E8VssLlF2GNDDigital GND(1.2 V)E9DMO1NE10DMO1POFVDDLSC2 PowerF2VssLSC3 PowerDDDDDDADData lane 1Digital MIPl outputLow LevelconnectionData lane 1Digital MIPI outputLow LevelconnectionDigital power supply (1.2 V)Digital power supply (1.2 v)F3VopHCMPowerAnalog power supply(2.8 V)F8INCKInput clockDMO3NDigital MIPl outputData lane 3Low LevelconnectionF10 DMO3PData lane 3Digital MIPI outputLow LevelconnectionG3VssHCPGNDAAnalog GND (2.8V)G8VssLSC2 GND D Digital GND(1.2V)G9VssMIF2 GNDD Digital GND (1.8VG10VoDMIFPowerDDigital power supply (1.8V)H1VDDLCN GND D Digital GND(1.2V)VsSLCNGNDDigital GND (1.2 VH3VopHCPPowerAnalog power supply(2.8VDLO2P( Pin for Sub-LVDS)Leave open(No connectionH9DLO2M000(Pin for Sub-LVDS)Leave open(No connectiH10DLOOP(Pin for Sub-LVDS)Leave open(No connection)VssHPX3 GND AAnalog GND(2.8 V)J3VoDHPXPowerDLO3PADDDAADDAnalog power supply(2.8 V)(Pin for Sub-LVDS)Leave open(No connectionDLO3MO00(Pin for Sub-LVDS)Leave open(No connection)J10DLOOMD(Pin for Sub-LVDS)eave open(No connection)K2VssLPL 1GNDDDigital GND(1.2V)K3 VDDLPL1 Power D Digital power supply(1.2V)K4VoDMIO Power D Digital power supply(1.8V)K5DLO1M(Pin for Sub-LVDS)Leave open(No connectionDLCKM0b「(Pin for Sub-LVDS)Leave open(No connection)Leave openK7DLCKPD(Pin for Sub-LVDS(No connectionLeave openK8DLO9PD(Pin for Sub-LVDS)(No connectionLeave openK9DLO9M(Pin for Sub-LVDS)(No connectionK10DLO5P(Pin for Sub-LVDS)Leave openNo connection
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