88E1116R_Datasheet
88E1116R_Datasheet，marvell以太网phy芯片手册，全本88E1116RM A RV E LL. Alaska Gigabit Ethernet TransceiverOVERVIEWFEATURESThe Alaska 88E1116R Gigabit Ethernet Transceiver is10/100/1000BASE-TIEEE 802.3 complianta physical layer device containing a single GigabitSupports reduced pin count GMII(RGMID)interfaceEthernet transceiver. The transceiver implements theFour RGMii timing modesEthernet physical layer portion of the 1000BASE-T,100BASE-TX. and 10base-t standards. t is manufacIntegrated mdi interface termination resistors thateliminate twelve passive componentstured using standard digital CMOS process and con-tains all the active circuitry required to implement theEnergy Detect and Energy Detect+ low powerphysical layer functions to transmit and receive data onmodesstandard Cat 5 unshielded twisted pairThree loopback modes for diagnosticsThe 88E1116R device has two regulators to generateDownshift"mode for two-pair cable installationsall required voltages. The 88E1116R device can beFully integrated digital adaptive equalizers, echopowered by a single 1.8V, 2.5V, or 3. 3V supply Alternacancellers, and crosstalk cancellerstively, if the regulators are not used, then the 88E1116RAdvanced digital baseline wander correctiondevice can be powered by a 1. 8v and 1.2V supplyAutomatic MDi/MDIX crossover at all speeds ofThe 88E1116R device incorporates the Marvell@ VirtualoperationCable Tester (VCTTM)feature, which uses TimeAutomatic polarity correctionDomain Reflectometry(TDR)technology for the remotelEEE 802. 3u compliant Auto-Negotiationidentification of potential cable malfunctions, thusSoftware programmable LEd modes including LEDreducing equipment returns and service calls. UsingtestingVCT, the alaska 88E1116R device detects and reportspotential cabling issues such as pair swaps, pair polar-Supports IEEE 1149.1 JTAGity and excessive pair skew. The device will also detectMDC/MDIO Management Interfacecable opens, shorts or any impedance mismatch in theCRC checker, packet countercable and reporting accurately within one meter the disPacket generationtance to the faultVirtual Cable Tester(VCT)The 88E1116R device integrates MDI interface terminaAuto-Calibration for MAc Interface outputstion resistors into the Phy. this resistor integrationComa Mode supportfacilitates board layout and reduces board cost byRequires a single 1.8v supplyreducing the number of extenal components. The new10 pads can be supplied with 1.8V, 2.5V, or 3. 3VMarvell calibrated resistor scheme will achieve andexceed the accuracy requirements of the IEEE 802.3Two regulators generate all required voltagesRegulator can be supplied with 1.8V,2.5V or 3.3Vreturn loss specificationsCommercial gradeThe 88E1116R device supports the reduced gmll64-Pin QFN package(RGMI)for direct connection to a MAC/Switch portThe 88E1116R device uses advanced mixed-signal processing to perform equalization, echo and crosstalkcancellation, data recovery, and error correction at agigabit per second data rate. The device achievesrobust performance in noisy environments with very lowpower dissipationThe 88E 1116R device is offered in a 64-pin QFn pack-The 88E1116R device is footprint compatible with the88E1116 device As the 88E 1116R device employs integrated MDi interface terminations, all external mDIinterface termination resistors and capacitors must beremoved when migrating from the 88E1116 to88E1116R. See 88E1116 to 88E1116R Migration Appli-cation note for more detailsCopyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 388E1116RMARVELLo Alaska Gigabit Ethernet TransceiverMagnMedia Types10/1001000Mbps88E1116R|a盖10BASEEthernet macRJ-45Device100BASE-TX1000BASE-TMAC InterfaceRGMII88E1116R Device used in Copper ApplicationDoc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 4Document Classification: Proprietary InformationMarch 1. 2007. AdvanceTable of contentsSECTION 1. SIGNAL DESCRIPTION1.1 Pin Description101.1.1 Pin Type Definitions1264 Pin QFN Pin Assignment List- Alphabetical by Signal Name.……,…,,…,161.3 O State at Various Test or reset modes .mmm.,17SECtION 2. FUNCTIONAL SPECIFICATIONS2.1 Copper Media Interface..国面画192.2 MAC Interface(RGMII)4192.2.1 10/100 Mbps Functionality2.2.2 TX ER and RX ER Codingaaaaaiiaia t23Lo。 pback……………,….….….,.,…….…,…,….….……,…….……………212.3.1 MAC Interface Loopback212.3.2 Line Loopback.222.3.3 EXternal Loopback24 Synchronizing F|FQ….…,,…,…,,,,,,…,,,,,…,,,…,,,,…,……242.5 Copper Media Transmit and receive Function.man..m日a252.5.1 Transmit side Network Interface252.5.2 Encoder2.5.3 Receive Side Network Interface2.5. 4 Decoder2.6 Regulators and Power Supplies282.6.1 AVDD2.6.2 AVDDC282.6.3 AVDDR292.6.4 AVDDX2.6.5DVDD…292.6.6 VDDO26.7 VDDOR.292.7 Power Management302.7.1 Low Power Modes2.72 Low Power Operating Modes……2.7.3 RGMl Effect on Low Power modes3228Auto- Negotiation.........……33Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 588E1116RMARVELL Alaska Gigabit Ethernet Transceiver2.9 Downshift Feature…352.10 Advanced virtual Cable Tester362.10.1 Maximum Pe2.10.2 First Peak372.10.3 Offsetp2. 10. 4 Sample Poin2.10.5 Pulse Amplitude and Pulse Width392. 10.6 Drop Link...392.10.7 VCTTM With Link Up392.11 Data Terminal Equipment (DTE)Detect........2.12 CRC Error Counter and frame Counter412.12. 1 Enabling the crc error counter and frame counter.412.13 Packet generator412.14 MDI/MDIX Crossover422.15P。 olarity Correction..…432.16LED,,,,,,,,,,,…,…,,442.16.1 LED Polarity452.16.2 Pulse Stretching and Blinking.462. 16.3 Bi-Color LED Mixing472.16.4 Modes of Operation482.17 EEE 1149.1 Controller522.17.1 BYPASS Instruction522.17.2 SAMPLE/PRELOAD Instruction.52217.3 EXTEST Instruction552,17.4 The clamP Instruction552,17.5 The high-z Instruction552.17.6 ID CODE Instruction552.18 Interrupt.552.19 Automatic and Manual Impedance Calibration.……,…,…,…,…,…,…,……562. 19. MAC Interface calibration circuit562.19.2 MAC Interface Calibration Register Definitions2. 19.3 Changing Auto Calibration Targets2. 19. 4 Manual Settings to The Calibration Registers“““582.20 Configuring the 88E1116R Device..2.20. 1 Hardware Configuration612.20.2 Software Configuration-Management Interface632.21 Temperature sensor64Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellDocument Classification: Proprietary InformationMarch 1. 2007. AdvanceSECTION 3 REGISTER DESCRIPTION65SECTION 4, ELECTRICAL SPECIFICATIONS1104.1. Absolute Maximum Ratings,…,…,…,…,,…,…,…,…,…,…,,…,…,……,1104.2. Recommended Operating Conditions..,,.,……,,……1114.3. Package Thermal Information.………….……….…………1124.3.1 Thermal Conditions for 64-pin QFn Package1124. 4. Current Consumption...........面量量…1134.4.1 Current Consumption AVDD..1134.4.2 Current Consumption AVDDC..1134.4.3 Current Consumption AVDDR1144.4.4 Current Consumption AVDDX1144.4.5 Current Consumption DVDD4.4.6 Current Consumption VDDo1154.4.7 Current Consumption VDDOR1154.4.8 Current Consumption Center Tap1154.5. DC Operating Conditions1164.5.1 Non-RGMlI Digital Pins1164.5.2 Internal resistor Description4.5.3 Stub-Series Transceiver LogIc (55/.21174.5 4 EEE DC Transceiver Parameters1194.6. AC Electrical Specifications1204.6.1 Reset Timing ..1204.6.2 XTAL IN/XTAL OUT Timing1214.6.3 LED to CONFIG Timing1214.7 RGMII Interface Timing……,,…1224.7.1 RGMl AC Characteristics4.7.2 RGMII Delay Timing for different RGMiI Modes1234.8. MDC/MDIO Timing…12549. JTAG Timing…,,…1264.10.EEE AC Transceiver parameters1274.11. Latency Timing........….…1284.11.1 RGMII to 1000BASE-T Transmit Latency Timingaa“aa1284.11.2 RGMII to 100BASE-TX Transmit Latency Timing1284.11.3 RGMiI to 10BASE-T Transmit Latency Timing4. 11. 4 1000BASE-T to RGMll Receive Latency Timing1304. 11.5 100BASE-TX to RGMII Receive Latency Timing.1304.11.610 BASE-T to RGMll Receive Latency Timing……….….…………,130SECTION 5. PACKAGE MECHANICAL DIMENSIONS1315.1 64-Pin QFN Package...131Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 788E1116RMARVELL Alaska Gigabit Ethernet TransceiverSECTION 6. ORDER INFORMATION1336.1 Ordering Part Numbers and Package Markings1336.1.1 RoHS 5/6 Marking Example1346.1.2 RoHS 6/6 Marking Example135Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 8Document Classification: Proprietary InformationMarch 1. 2007. AdvanceSignal DescriptionSection 1. Signal DescriptionThe 88E1116R device is a 10/100/1000BASE-T Gigabit Ethernet transceiverFigure 1: 88E1116R Device 64-Pin QFN Package(Top view)文gg9廿廿廿廿廿廿凵廿廿廿凵廿守令导好寸守哥导$85#將RX CTRL4932TSTPTRXDIO5031MDIPIORXD[51EPAD-VSS30d MDIN[O]VDDOR52290 AVDDRX CLK5328叫NCRXD[2]54AVDDRXD]5526MD|P[1VDDOR56VREF57MARVEL L③24E MDIP[2TXD0]□5823MDIN[2TXD[1]B5988E1116R22AVDDTX_CLK F6021AVDDTXD[2Top ViewMDIP[3TXD3]□62190 MDIN[3]TⅩCTRL6318□NCCONFIG[O]64CTRL18三s回口cc×O百口口艺艺安安Copyright o 2007 MarvellCONFIDENTIALDoc. No. MV-S104224-00 RevMarch1.2007. AdvanceDocument Classification: Proprietary InformationPage 988E1116RMARVELL. Alaska Gigabit Ethernet Transceiver1.1 Pin Description1.1.1 Pin Type DefinitionsPin Ty peDefinitionHInput with hysteresisVOInput and outputInput onlOutput onlPUIntemal pullPDInternal pull downOpen drain outputTri-state outputADC sink capabilityDoC. No. MV-S104224-00 RevCONFIDENTIALCopyright o 2007 MarvellPage 10Document Classification: Proprietary InformationMarch.2007. Advance
- 2020-12-03下载
- 积分：1
基于fpga的自适应滤波器
关于自适应滤波器的fpga实现，对于想学数字滤波器的和fpga的同学来说非常好基于FPGA的自适应滤波器设计摘要数字滤波器较模拟滤波器相比,具有信噪比髙,过渡带性能好,髙可靠性及可扩展性,设计灵活方便的优势,应用范围越米越广。随着专用数字信号处理芯片的发展,数字滤波器的可实现性能以及处理速度得到了极大的提升,FPGA(现场可编程门阵列)作为一种新型数字信号处理芯片,具有数字信号处理速度快、数据并行处理并且利用硬件编程语言直接进行硬件设计等特点,自适应滤波器的FPGA设计以及优化方法,是目前的一个研究热点。本文对自适应滤波器进行 Matlab仿真,以对其结构特性以及运算特点进行了解,利用 Matlab生成测试信号与FPGA仿真软件 Modelsim进行联合设计以及行为仿貞,采用 Altera公司的 Cyclone IV系列芯片EP4CE15F17C8为载体的开发板进行设计仿真,在设计过程中,充分利用FPGA可以并行处理以及快速的数字信号处理的特点进行针对性的结构设计。在此基础上做了以下工作。在充分了解滤波器,自适应横向滤波器,自适应陷波滤波器以及FFT变换原理的基础上,选择并搭建∫设计平台,在目前自适应横向滤波器的FPGA设计的研究基础上,采用模块化的设计方法,单独设计可重复调用的串行FR滤波模块以及串行LMS杖值更新模块,对两种模块的设计以及综合分别进行了设计以及仿真实验,通过并行调川两种不同模块,每种调用四个的方式设计一个16阶的滤波器为例来阐述模块化设计方法,并设计32阶64阶分别与仝串行以及仝并行设计方式的处理速率以及逻辑资源调用进行比较,结果说明运算速率与并行调用模块数量成正比,远快于全串行结构的设计方式,并且对于64阶仝并行系统来说,极大的减少了硬件资源的消万方数据耗,提髙了设计灵活性。在此设计的基础上,针对传统自适应陷波滤波器的滤波频夲固定不变的缺陷,提出了一种频域变换法检测噪声特征频夲,并可以根据特征噪声频率实时改变陷波频率的滤波器设计方法,为了减小设计复杂性,研究了符号LMS自适应陷波器算法,通过 Matlab仿真实验选取符号的特征变量。并对噪声信号提取算法进行了介绍和设计仿真,最终设计出根据噪声频率自动调节陷波中心频率的自适应陷波滤波器,并对滤波器性能进行了 Modelsim仿真研究,自适应陷波器具有能有效的滤除对应频的单频噪声信号,并且根据噪声的频率特性自动调节滤波频率的特点。针对两种自适应滤波器的FPGA设计,体现了FPGA在自适应滤波器设计时灵活性以及针对性,两种不同类型的自适应滤波器,可以分别适用于普通数字滤波器无法有效发挥作用的场合,同时本文的设计方法对其它类型数字信号处理系统的FPGA实现具有一定参考价值关键词:现场可编程门阵列,自适应横向滤波器,模坎化设计,自适应陷波器万方数据DESIGN OF ADAPTIVE FILTER BASED ON FPGAABSTRaCTCompared with analog filter, digital filter has the advantages of high signalto noise ratio, good performance of transition zone, high reliability andexpansibility, flexible and convenient design and application With developmentof special digital signal processing chip, digital filter Can achieve performanceand processing speed has been greatly improved, the realization of the use of thebetter performance of digital chip design more complex filter, so that the adaptivefilter realization and application become possible, FPGA (field programmablegate array) is a new type of digital signal processing chip, with parallel processingof data and Can use hardware programming language directly the characteristicsof the hardware design, is currently a hot research topic for study of adaptive filteris implemented on FPgaThe matlab simulation of the adaptive filter to understand the characteristicsof the structure and opcration characteristics, and the use of Matlab generatingtest signals and FPGA simulation software Modelsim joint behavior simulation ofFPGa design, then to Altera cyclone Iv series chip ep4cel5f17c8 as the carrierof the development board for simulation design. in the design process, make fulluse of FPGa parallel processing and fast digital signal processing for structuraldesign On this basis, the following work has been doneThe filter needed to fully understand, adaptive transversal filter, adaptivenotch filter and Fft transform based on the principle of selection and build adesign platform, first in the basic research of current FPGA adaptive transversalfilter realization, using modular design method, the structure is divided into singleand serial FiR filter module serial LMS weight update module, the design of thetwo modules and integrated were designed, and simulation experiments, through万方数据the parallel call two different modules, each call the four way to design a 1 6 orderfilter as an example to illustrate the modular design method, and design of 32order and 64 order respectively with serial and the processing rate parallel designmethods and logic resources call were compared. The results show that theoperation rate and parallel call module is proportional to the number, far faster Inthe whole serial design mode, and for the 64 order all parallel system, greatlyimprove the design flexibility, reduce the consumption of hardware resourcesAfter the design on this basis, the traditional adaptive trapped wave filter, filterfrequency fixed defects, put forward a method of frequency domain transformdetection noise characteristic frequency, and can change in real time accordingto the characteristics of noise frequency trapped wave frequency filter designmethods, in order to reduce the design complexity and the sign LMs adaptivenotch filter algorithm, the characteristic variables of the symbol is determinedthrough the simulation experiment of Matlab. And the noise signal extractionalgorithm are introduced and the simulation design, the final design according tofrequency noise automatically adjust the trapped wave frequency adaptive notchfilter, and on the performance of the filters were Modelsim simulation researchthe adaptive notch filter has CaN effectively filter on the frequency of the singlefrequency noise signal, and does not affect the characteristics of waveforms usefulFor the fpga design of two based on the lms adaptive algorithm of filterreflecting the FPGa in the adaptive filter design flexibility and uniqueness, twodifferent types of adaptive filter can be respectively applicable to ordinarydigital filter Can not effectively play the role of occasions, also the designmethod of other types of digital signal processing system based on FPGaimplementation has a certain reference valueKEY WORDS: FPGA, Adaptive transversal filter, Modular design, Adaptivenotch filter万方数据目录摘要ABSTRACT··,··*···第·章绪论…1.1研究目的与意义1.1.1数字滤波器简介·················+··*····+··········*···:··.*····…···*········:··+*·········1.1.2基于FPGA的自适应滤波器研究意义·“中,非2国内外研究现状1.2.1自适应滤波器研究现状122自适应滤波器的FPGA实现研究现状·······申中···申1.3课题的主要研究内谷··B申61.3.1课题的主要工作1.3.2课题的研究实现方案…4本章小结第二章自适应陷波滤波器的原理以及实验平台2.自适应滤波器理论介绍·····中中·········中·中·"中··中·中····中····申2.1.1IR与FIR滤波器简介2.12LMS算法原理132.1.3自适应陷波器的原理15214FFT变换的原理··p··中··中··,和p申·和中中····中·申22设计平台介绍2022.1自适应滤波器的设计平台20222自适应陷波滤波器接2223本章小结24第三章自适应横向滤波器的FPGA实现..273.1自适应滤波器的 Matlab仿真研究…····中中中申·中申···申申p中申·中申··申p申中273.1.1自适应滤波器的功能仿真研究273.2自适应滤波器的滤波收敛性能研究方法…83.1.3自适应滤波器的收敛性能研究….30万方数据3.2自适应滤波器的FPGA模块化设计333.2.1自适应滤波器FPGA模块化设计原理333.22FIR串行模块的设计申·中p申申,申申申·申和中p申申非申·p;申p申·非申·申新申中和申p申和·申·申P申申·申申申p申p343.2.3LMS串行模块的设计35324自适应滤波器多级处理结构整体设计363.2.5结构特性分析393.3木章小结···非中中非第四章自适应陷波滤波器的FPGA设计41符号LMS算法的梯度特征值选择及系统结构设计.414.1.1符号LMS算法的梯度特征值选择4141.2FIR自适应陷波滤波器系统结构设计42噪声信号分析以及参考信号频率值提取……1464.2.1FFT变换的功能464.2.2FFT变换的参数介绍42.3 FFT IP核的调试以及功能测试……4842.4特征噪声频率提取算法.…43自适应陷波模块的设计非··申申中431自适应波器的 Matlab仿真43.2自适应陷波器FPGA设计时的数据截取方法554.3.3白适应陷波器模块的FPGA设计56434自适应陷波器的整体设计6044采用频域变换法自适应陷波器滤除工频噪声.44.1提高系统实时性的方法6144.2模拟与实验验证45木章小结·········65第五章总结与展望DD67参考文献致谢75攻读学位期间发表的学术论文目录77ⅤI万方数据太原理工大学硕上饼究生学位论文第一章绪论1.1研究目的与意义滤波器从1917年发明以米,已经有近一个世纪的发展史1,滤波器的发明也极大的推进了电了器件以及通信的发展。计算机技术以及集成电路的技术的发展又使滤波器产生飞跃式的发展,各科数字电路以及模拟开关电路元件体积越来越小,密度越来越高,直接催生了集成芯片式RC有源滤波器,开关电容滤波器以及数字滤波器。使滤波器的应用范围再一次扩大,不仅仅在通信领域,在医学,电气,图像处理等领域也起到了举足轻重的作用。1.1.1数字滤波器简介数字滤波器作为数字信号处理的一部分,是随着计算机以及数字器件的发展而发展起来的一门比较新的技术,尤其近几年来,数字处理芯片以及数字信号处理技术的发展使得数字滤波器的优点越米越突出,现代数字滤波器可以轻易实现将过渡带缩短到Iz以內,这点是模拟滤波器无法达到的性能指标。数字滤波器比模拟滤波器还有更优越的信噪比、可靠性以及灵活性和可扩展性,并且随着数字集成电路的发展,制作成本将会越来越低S。目前使用比较多的滤波器设计方法分别是无限冲击响应(IR)以及有限冲击响应(FR)波器,其屮由于FR滤波器可以很容易实现具有严格线性相位结构的滤波器,而IR滤波器要达到严格线性相位结构必须经过仝通网终线性相位矫正从而大大增加滤波器的阶数。FR滤波器由于其冲击响应有限,所以是个稳定系统。并且没有反馈环节,有利于其在使件上实现。所以FR滤波器以其独有的优势应用于线性相位结构的系统屮。近几年米,随着RLS以及LMS自适应算法的提出S,很多专家学者提出了利用自适应算法在数字系统上设计自适应滤波器,使滤波器的性能更加灵活,并且在对滤波器有特殊滤波要求的场合使用門,例如自适应陷波器常用在电气设备中滤除工频干扰而对其余频率信号几乎完全不产生影响,以及在通道失配屮采用自适应滤波原理进行矫正12,有些系统可以采用自适应算法达到抵消噪声千扰3,这些都是常规滤波器无法达万方数据基于FPGA的自适应滤波器设计到的性能指标。LMS算法以其简单的特性,可以在多和数字芯片上进行设计。尤其在FPGA上实现各种自适应滤波器14,是目前针对自适应滤波器方面的一个研究方向。1.1.2基于FPGA的自适应滤波器研究意义FIR与IR滤波器都是数字滤波器,即在数字系统上实现滤波器功能,而数字系统又分为软件数字系统实现以及硬件数字系统实现,软件数字系统实现最常用的例如使用MEATLAB或者 Labview进行编程实现15,其优点是可以自如的调节信号字长以及滤波步长,可以达到很高的精度,并且可以综合其它的处理功能为一体。缺点是接口比较单,必须接外置的采集卡,需要以计算机为载休休积往往很大。并且对信号的处理速度在相同糸件下要比硬件实现的滤波器系统要慢,并不能达到很好的实吋性,实际应用中只适用于屮、少量的数据后期分析以及对成本以及实时性要求不高的一些系统使用16。哽件芯片实现的数字滤波器实吋性要比PC杋软件好,并且硬件载体也比较多,如单片机、ARM类芯片,和专门用于数字信号处理的DSP芯片上均可以实现滤波器功能,但是其运算均为串行运算,(现场可编程门阵列)FPGA作为·种可编辑器件,不仅能实现上述所有芯片的功能,在资源配置合理的情况下,还能进行处理馍垬多重并行调用,即在个芯片上实现多个基本芯片同时处理的功能8,从而达到特别优异的数字信号处理功能,目前在图像处理等需要实时对大量数字信号进行滤波处理的领域,FPGA已经成为款不可或缺的芯片。但硬件设计数字滤波器的时候,山于数字滤波器的特殊性,在设计数字滤波器的时候,并没有现成的标准公式,这造成了很多数字滤波器并不能完全直接在硬件系统上实现,例如,FR数字滤波器,必须先利用软件工具得出FIR滤波器的各延迟抽头系数才能进行硬件设计,所以设计FIR滤波器的时候,是离不开计算机系统的,但是设计好的滤波器,可以脱离软件系统进行使用。由亍FR滤波器的本质就是一个标准的乘加运算集,恰好可以利用分布式算法实砚FIR滤波器,分布式算法的每个乘法运算屮必须有一个乘数为常数,这又与FPGA的基本逻辑单元査找表的功能相适应,利用査找表结构可以进行个常数乘数与·个变量相乘的运算,这样在实现FIR滤波器的时候,利用分布式算法,可以实现不使用或仅使用少量乘法器资源即可完成FR滤波器结构设计,FPGA的设计结构刚好与FIR滤波器的万方数据
- 2021-05-06下载
- 积分：1
