Hilbert-Huang Transform and Its Applications

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《ANSYSWorkbench设计、仿真与优化》以最新版ANSYSWorkbench11.0为依据，以工程人员产品设计的流程为主线，由浅入深地介绍了ANSYSWorkbench在产品设计、仿真与优化过程中的具体功能、使用方法和应用实例。ⅣANSYS Workbench设计、仿真与优化4.2.1基础…………484.2.2分析关键………494.2.3分析步骤……………………………………494.3振动电机轴谐响应分析……………….544.3.1基础………………54………54.3.3分析步骤……………………………………………………………554.4机柜随机振动分析…………………………………………………………614.4.1基础……………………………………………………………614.4.2分析关键…………………………………………………624.4.3分析步骤………………………………………………………62第5章机构运动学分析…………………675.1机构运动学分析基础………………………………………………………675.2轻型打桩机机构运动学分析……………………………………685.2.1工程背景……………………………………………5.2.2分析关键…………………………………………685.2.3分析步骤…………69第6章热力学分析………………………………………756.1热分析基础…………………………………………………………756.2汽缸盖稳态温度场分析……………………………………………766.2.1工程背景766.2.2分析关键………………………………………………………776.2.3分析步骤……………………………………776.3涡轮增压器涡壳瞬态温度场分析和热应力分析………………………………806.3.1工程背景………………………………………………806.3.2分析关键………6.3.3分析步骤…………………………81第7章疲劳分析……………………………………………………867.1疲劳分析基础……………………………………:867.1.1疲劳分析定义……………………………………………867.1.2 AWE Fatigue程序处理疲劳问题的过程………………862按键疲劳分析………………………………………………………877.2.1工程背景………………………………………………………877.2.2分析关键…………………887.2.3分析步骤…………………………………………………887.3轮毂疲劳分析………………………………………………………………92日录7.3.1工程背景………927.3.2分析关键………27.3.3分析步骤……93第8章优化设计……………………………………………………………………968.1优化设计基础……………………………………………968.1.1优化设计的基本原理…968.1.2优化设计的分类………………………………………………………978.1.3AWE优化设计的分析步骤………………988.2支架拓扑结构优化设计………………………………………………………998.2.1工程背景………8.2.2分析关键…………………………………………998.2.3分析步骤…98.3散热器形状优化设计……………………………………………………………1028.3.1工程背景………………………………………………………1028.3.2分析步骤…………………103第9章二次开发1109.1二次开发基础………………………………………………………11109.2参数化程序设计语言……………………………………………………1109.2.1APDL简介…………………………1109.2.2APDL的参数和宏………………………………………………1119.2.3气动刹车装置非线性分析12…………………………119.3用户操作向导……………………1159.3.1 Wizard简介…………………………………………………………1159.3.2操作向导编辑器…………………………………11169.4客户化定制…………1179.4.1SDK简介………………………………………………………………1179.4.2客户化定制实例…………………………………………………118第1章 ANSYS Workbench基础1.1 ANSYS Workbench概述随着计算机辅助工程(CAE)技术在工业应用领域中的广度和深度的不断发展,它在提高产品设计质量、缩短周期、节约成本方面发挥了越来越重要的作用。目前,CAE分析的对象已由单一的零部件分析拓展到系统级的装配体,如飞机、汽车等整机的仿真。同时,其分析的领域已不再仅仅局限于结构力学,已涉及流体力学、热力学、电磁学、多场耦合等更加丰富的物理空间。而且,CAE分析不再仅仅是专职分析人员的工作,设计人员参与CAE分析已经成为必然ANSYS Workbench Environment(AwE)作为新一代多物理场协同CAE仿真环境,其独特的产品构架和众多支撑性产品模块为产品整机、多场耦合分析提供了非常优秀的系统级解决方案。它所包含的3个主要模块:几何建模模块( Design Modeler)、有限元分析模块( Design Simulation)和优化设计模块( Design Xplorer)将设计、仿真、优化集成于一体,可便于设计人员随时进入不同功能模块之间进行双向参数互动调用,使与仿真相关的人、部门、技术及数据在统一环境中协同工作。具体来讲AWE具有的主要特色如下。1.强大的装配体自动分析功能针对航空、汽车、电子产品结构复杂,零部件众多的技术特点,AWE可以识别相邻的零件并自动设置接触关系,从而可节省模型建立的时间。而现行的许多软件均需要手动设置接触关系,这不但费时同时还容易出错。除此之外,AWE还提供了许多工具,以方便手动编辑接触表面或为现有的接触指定接触类型。AWE提供了与CAD软件及设计流程之间的无与伦比的整合性,从而发挥CAE对设计流程最大限度的贡献。最新的AWE使用接口,可与CAD系统中的实体及曲面模型双向连接,具有更高的CAD几何导入成功率。当CAD模型变化时,不需对所施加的负载和支撑重新定义。AWE与CAD系统的双向相关性还意味着,通过AWE的参数管理可方便地控制CAD模型的参数,从而提高设计效率;AWE的这一功能,还可对多个设计方案进行分析,自动修改每一设计方案的几何模型。2.自动化网格划分功能许多CAE用户都花大部分的时间在建立网格上,AwE在大型复杂部件,如飞机组装配件的网格建立上独具特色,自动网格生成技术可大大节省用户的时间。根据分析类型不同,有很多因素影响分析的精度。传统的专业分析人员花大量的时间和训练来掌握各种分析,手动处理模型以保证分析的精度;而对于设计人员来讲,他所关注的应该是自己的产品设计,而不是有限元方法,因此需要一个可靠的工具来替代传统的工具,尽可能实现自动化。AWE的自动化网格划分功能如下:自适应网格划分,对于精度要求高的区域会自动调整网格密度ANSYS Workbench设计、仿真与优化·自动化网格划分,生成形状、特性较好的元素,保证网格的高质量。·自动收敛技术,是自动迭代过程,通过自适应网格划分以使指定的结果达到要求的精度。例如,如果对装配中某一个零件的最大应力感兴趣,可指定该零件的收敛精度。·自动求解器选择,AWE根据所求解问题的类型自动选择适合的求解器求解。智能化的负载和边界条件自动处理。3.协同的多物理场分析环境及行业化定制功能CAE技术涵盖了计算结构力学、计算流体力学、计算电磁学等诸多学科专业,而航空产品的设计对这几个学科专业都有强烈的CAE需求。单个CAE软件通常只能解决某个学科专业的问题,导致使用者需要购买一系列由不同公司开发的、具有不同应用领域的软件,并将其组合起来解决其实际工程问题,这不但增加了软件投资,而且很多问题会由于不同软件间无法有效而准确地传递数据而根本不能实现真正的耦合仿真计算。目前,全面的、真正的“多物理场耦合分析”(如图1.1所示)时代已经来临,多场分析能力已经成为现代CAE软件技术水平的重要标志。多组分/多相流}(流体力学)[可压缩流H高级辐射高级疲劳高度非线性共轭传热结构力学多物理场耦合(温度场非线性非线性/辐射时/频域动力稳态/瞬态线性静力低频电磁场}(电磁场)M高导/对流图1.1现代高级CAE软件AWE组合分析能力4.快捷的优化工具 DesignXplorerAWE本身既是一个成熟的多物理场协同CAE仿真平台,又是一个基于最新软件技术的开放式开发平台,利用其开发包 Workbench SDK可以非常便捷地实现诸如专用程序开发、流程自动化和简化、专家经验的保存和固化、分析规范的保存和固化、自有程序的包装、其他程序的集成等众多的用户化开发功能。在 Workbench基础上,设计与分析间的关系就简化为:·分析部门(或人员)根据需求为设计部门量身定做各种特定产品的专用分析程序,这些程序融专家经验、自有程序、分析规范等为一体,完全专用化和自动化,一次定制,终身受益;设计部门(或人员)在针对性极强的专用程序上轻松实现设计分析-优化评价等工作;AWE多物理场协同仿真环境充分体现了 ANSYS公司“面向实实在在的工业需求,以技术为本,以优化用户产品研发流程为目标,为用户提供完整CAE解决方案”的宗旨。在AWE环境下,整个CAE应用的方式和意义都将发生革命性的变化。仿真分析的目的是优化产品性能,AWE/ DesignXplorer是基于DSDB数据库文件的参数优化工具,结合CAD系统/AGP和 Design Space/AWE进行优化:在CAD系统/AGP中第1章 ANSYS Workbench基础3·进行参数化建模,在 Design Space或AWE中进行初步的分析,并确定感兴趣的参数,在DesignXplorer中进行参数优化优化参数可以是CAD模型的几何参数、结构形式、施加的边界条件、求解得到的分析结果等,也可以是由这些参数进行数学运算后派生出来的参数,既可以进行连续性参数和离散化参数的优化,又可以进行单目标或多目标的优化,得到设计空间的三维设计响应面/二维设计曲线,并自动根据优化结果更新几何模型文件。因此,作为新一代多物理场协同CAE仿真环境,AWE以其独特的产品架构和众多支撑性产品模块已为越来越多的产品提供了非常优秀的系统级解决方案1.2 ANSYS Workbench产品设计流程和文件格式1.2.1 ANSYS Workbench产品设计流程AwE提供一个集成统一的仿真环境帮助工程人员完成产品CAE开发的全过程。在AWE环境下,典型的项目开发,包括以下模块:DesignModeler,几何建模和CAD模型导入模块;Design Simulation,结构、热和电磁有限元分析模块;Design Xplorer,最优化设计模块。AwE统一的开发环境以及具有攀升化的设计方案,帮助企业真正实现产品设计仿真到优化的协同。其中, Design Simulation与CAD系统之间可进行双向模型参数互动、可将 ANSYS嵌入CAD运行环境,使用CAD环境中的几何模型的链接,不存在模型转换失真的棘手问题。同时, Design Simulation从CAD中导入装配体时可以自动建立装配接触关系。这样,设计人员可以在 Design Simulation中进行零件以及装配体性能的初步快速分析,并确定感兴趣的区域和性能,再利用 Design Simulation中高端CAE仿真工具和疲劳分析模块一 Fatigue Module对产品强度、动力学特性以及疲劳寿命进行深入的认知,确定优化设计参数,最后在多目标优化模块一 Design Xplorer中同步优化参数,改进产品设计。软件系统的主框架如图1.2所示。ANSYS WorkbenchDesignModelerE Design Simulation Design Xplorer图1.2AWE系统框架图除了上述的主要流程模块之外,AWE还包括以下辅助模块:Engineering Data,用于设定材料和载荷加载信息;FE Modeler,用于输入来自 NASTRAN, ABAQUS,或 Design Simulation所建立的网格模型,作为 ANSYS有限元分析的输人,它也能将网格模型反演生成几何模型;ANSYS AUTODYN,爆炸、冲击等结构显式动力学分析模块。ANSYS Workbench设计、仿真与优化1.2.2文件格式AWE中涉及的主要文件的类型及格式如表1.1所示表1.1AWE中文件格式说明文件名类型说明obname, wbdbWorkbench项目数据库文件,用于管理项目中的不同类型模块文件bname agdbDesign Modeler数据库文件,用于存储几何模型信息jobname cmdbCFX- Mesh数据库文件,用于存储流体网格信息jobname dsdbDesign Simulation数据库文件,存储结构、热和电磁仿真中的所有模型信息obname, edbEngineering Data数据库文件jobname fedbFE Modeler数据库文件,用于存储从 NASTRAN或 DesignSimulation输入的网格信息jobname adANSYS AUTODYN数据库文件,用于存储显式分析软件 AUTODYN必需的信息jobname ddbDesignXplorer数据库文件,用于存储优化方程中设计参数和目标参数的关联信息13安装和起动配置1.3.1 ANSYS Workbench11.0安装安装 ANSYS Workbench1.0前需要将 Windows2000打SP2补丁( Windows XP打SP1补丁),并安装IE6.0以上。另外,系统的日期和时间,要是当前的日期和时间。具体的安装步骤如下。(1)放入安装光盘,在弹出的“ ANSYS DVD Launcher”窗口中,选择“Next”,进入下一级安装窗口,如图1.3所示。ANSYS Products 11.0for Windows 32-bitOperating SystemsANSYS图1.3 ANSYS DVD Launcher窗口1第1章 ANSYS Workbench基础(2)在弹出窗口(如图1.4)中,选择安装的产品“ ANSYS Products”,并在接下来的安装语言窗口,选择“ English”,进入下一级安装界面。ANSYS ProductsInstall ProductsANSYS AA图1.4 ANSYS DVD Launcher窗口2(3)在图1.5所示的弹出窗口中,选择“ L AGREE”后,单击“Next”,进人到下一级安装界面ANSYS需oLGRIEsiDoN et图1.5 InstallShield wizard窗口1(4)根据您的需求选择安装的路径(如图1.6),单击“Next”后进入到“ Select Installation Components"。(5)在图1.7所示的窗口中选择完毕后一直单击“Ncxt”,安装程序开始安装ANsYs11.0。(6)在图1.8所示的窗口中单击“ Finish”,完成软件安装。(7)回到步骤(2)中的“ ANSYS DVD Launcher”窗口,单击“ License Management”,出现下一提示画面(如图1.9),问是否是 license server machine,选择“是(Y)(8)出现下一提示画面(如图1.10),问是否有 license文件,选择“否(N)(9)出现下一提示画面(如图1.11),问是否继续安装,选择“是(Y)ANSYS Workbench设计、仿真与优化图1.6 Installshield wizard窗口2ANSYSwr图1.7 InstallShield Wizard窗口3ANSYS图1.8 InstallShield Wizard窗口4

altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation

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