船舶海上运动matlab仿真

米联的FPGA开发例程很详细二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍1Z702N南京米联电子出品1GB内存XC7Z020-CG484-1I型号:MiZ702N【MZ702升级】8 GB EMMC ARM A9双核■ARMA9双核667M■1024MB内存■8 GB EMMC(板载)a HDMI (ADV7511)RGM|千兆网口7000斯7m是2USB2.0高速■USB转串口VGA(565)输出TF接口音频接口■支持子卡核心板+底板高速接插件■专业电源管理第2页共1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍MiZZOIN南京米联电子出品1GB内存XC72010/020CLG400型号:MiZ70N【Mz701升级】8 GB EMMC ARM A9双核■ARMA9双核667M1024MB内存■8 GB EMMC(板载■HDMI10模拟)ARMF部中■RGM||千兆网口黑!zM770MD020Angor eacH■USB20高速■UsB转串口■TF接口翻aVGA(子卡)输出音频接口(子卡■支持其他子卡核心板+底扳高速接插件■专业电源管理第3页共1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍版本时间描述Rev1.02015-07-25第一版初稿Rey.12016-03-31更新26章节Rey.22016-04-10更新inux系统定制相关教程Rey.32016-04-31更新裸机部分23章及操作系统部分章节Rey1, 42016-05-08更新裸机部分24章及操作系统部分章节Rev1.52016-0605修复第15章自定义P生成的bugRev1.62016-06-21修复了第三章状态机的错误代码,提供了多个仿真例子Rev1.720160627重新调整了文誉结构内容排布更加合理增加了里利理论部分的代码分析Rey1.82016-07-12第三章中关于阻寒和非阻塞视频讲解概念混淆的纠正。REVt.92016-08-10增加OV725PvTG| P Video out|P使用讲解AX|- Strean协议和VDMA|P使用REV2,02016-08-14修改目录顺序把GA接口部分的讲解放到HDM之前讲解ⅫLNX自带的标准视频类P的使用包括 Video in ipDMA|P∧TCP∧ deo out ip给出了彩条测试,内存显示图片的测试。第4页1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍封装了OV7725自定义P实现图片显示封装了OV5640自定义P实现图片显示REV212017-0228重大更新对之前的例子进行了完善,并且增加了很多新例子,删除一些不必要,不常用的例子REV2.22017-05-10重大更新,第三季SOC裸机更新到17课时;第四季L|UX更新到第七课时;第五季节更新到11课时;大量实战例子第5页共1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍感谢您使用南京米联团队开发的MiZ7(MZ701NMZ702MIZ702N)开发板,在使用开发板前请认真阅读本手册,并且掌握如何正确使用开发板,不合理的操作会导致开发板损坏。此手册不断更新中,请下载最新版木。软什版本:ⅤVADO20154使用本手册提供的Ⅴ IVADO版本或者到赛灵思官网下载20154版本http://www.xilinx.com/support/download.html版权声明:木手册版权归南京米联电子科技有限公司所有,并保留一切权利,未经我司书面授权,擅自摘录或者修改本」册部分或者全部内容,我司有权追究其法律责任。技术支持:版主大神们都等着大家去提问-电子资源论坛www.osIc.cn微信公众平台:电子资源论坛第6页共1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍目录目录【第季】 ZYNQ SOC开机及FPGA基础共12课.25S01CHo1开机程序测试∴261.1MZ70N开机测试连线图61.2MZ702N开机测试连线图13MIZ702开机测试连线图1.5 UBUNTU系统界面……291.7网口测试18美图欣赏S0lCH02 ZYNQ VIVADO软件安装……2 1 VIVADO软件介绍.22ⅥVADO软件安装适合所有 vlado安装)23 VIVADO软件注册…23本章小结.888245S01CH03USB卜载器驱动安装及下载程序3.1下载器驱动的安装453.2下载 runed工程的bit文件验证板子和下载器工作正常..463.3下载器使用需要注意的问题.474IⅤ erilog HDL代码规范.项目构架设计.接口时序设计规范4842技术背景43 Verilog最最基础浯法…44关键字5545 Verilog中数值表示的方式46阻塞赋值和非阻塞赋值详解...61SOI CHO5FPGA设计 Verilog基础()5.1状态机设计52一段式状态机6753两段式状态机…54三段式状态机70S0lCH06FPGA设计 Verilog基础(三)61完成的 Test bench文件结构62时钟激励设计,,63复位信号设计756.4特殊信号设计…65仿真控制语句及系统任务描述66加法器的仿真测试文件编写.82SO1CHO7 FPGA RunLED创建VADO工程实验….85第7页共1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍7.1硬件图片7.2硬件原理图.…8573新建 IVADO工程.8674创建工程文件.,897.5 Verilog FPga流水灯实验937.6添加管脚约束文件7.7编译并且产生bit文件.78下载程序79实验结果…1007.10木章小结··;········;。·:101S01CH08 FPGa Button按钮去抖动实验8.1硬件介绍…10282时序设计1038.3程序源码.10384程序分析8.5综合布线前仿真时序10886 Chipscope在线逻辑分析仪仿真.10887输出结果…8.8小结108S01CH09FPGA多路分型器设计11091硬件图片.11092硬件原理图11093介于ⅤVADO的FPGA设计流程94多路分配器设计思想95时序设计1129,.6稈序源码.11297行为仿真117971创建多路分频器工程.11797.2添加仿真文件.121973行为级仿貞98综合 Synthesis1299.8.1添加文件98.2综合并查看报告..1319.8.3综合时序仿真13199执行 Implementation132991执行并查看报告132992布局布线后时序仿真……13390Ⅴ IVADO在线逻辑分析仪使用··4··量·非,。134910.1 IP Catalog添加 IA ip corc.…134910,2逻辑分析仪抓取的信号138910.3逻辑分析仪仗用…1399l1小结140s01CH10VGA接口测试141第8页共1185二三电子米联电子ww.orc. cn /ZYNO SOC修炼秘籍10.1硬件介绍…141102时序分析…····+··“···+114310.3新建Ⅴ IVADO工程.14410.4创建工程文件14910.5添加管脚约束文件..…16310.6编译并且产生bit文件169107下载程序10.8实验结果…17110.9本章小结.S01CH11ADV751 HDMI接口测试17311.1ADV7511概述111.1硬件特性111.2视频输入…17311.1.3支持的输出格式174111.4视频接口信号采样.111.5功能框图176111.6奇存器空间.17611.2硬件电路分析177l1.3创建工程文件17811.4添加管脚约束文件.18311.5编译并且产牛bit文件18711.6下载程序.18711.7实验结果189S0ICII12PLIO口模拟IDMI接口测试l90121创建工程文件……124添加管脚约束文件.12.5编译并且产生bit文件.201126下载程序…201127实验结果.203【第二季】 ZYNQ SOC入门基础共16课吋205S02CH1 Hello world实验2061.1最小系统分析2061.6 Memtest内存测试程序…2291.7 DRAMTeSt内存测试程序2311.8LWP协议对千兆网口测试19使用快捷按钮调试…2351.10本章小结S02CHO2MIO实验……21GPO简介362.1.lGPO的控制寄存器地址空间2372.12MO内部构造分析…240213EMIO的特性24l22电路分析及实验预期241第9页共1185

MATLAB风力发电的demo程序，包括风力发电系统的各个部分

IEEE14节点模型该模型基准容量为100MVA，基准电压为23KV，整个网络总负荷为28.7+7.75MVA.原模型有16条支路，但因为配网运行是开环运行，减去原有的14、15、16三条支路

ModBus-Modbus是由Modicon(现为施耐德电气公司的一个品牌)在1979年发明的,是全球第一个真正用于工业现场的总线协议。ModBus网络是一个工业通信系统,由带智能终端的可...

C语言课件，总共10章，包括概述、数据描述、输入输出、流程设计、数组、函数、预处理、指针、结构体与共用体、文件

MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. The material contained herein is4 provided on an"as iS basis and to the maximum extent permitted by applicable law, this material is5 provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIP6 hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not7 limited to, any (ifany)inplied warranties, duties or conditions of merchantability, of fitness for a8 particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of9 viruses, and of lack of negligence10 All materials contained herein are protected by copyright laws, and may not be reproduced, republisheddistributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express12 prior written permission of MIPI Alliance. MIPl, MIPI Alliance and the dotted rainbow arch and all related3 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and14 cannot be used without its express prior written permission15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET16 POSSESSION. CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH17 REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT.IN NO EVENT WILLI8 ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT9 OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE20 GOODS OR SERVICES. LOST PROFITS. LOSS OF USE. LOSS OF DATA OR ANY INCIDENTAL.21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH25 DAMAGES26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance30 with the contents of this Document. The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential

STM32f103C8T6枚举成HID设备与PC通信，速度实测可达64K/s,USB口D+需要上拉1.5K电阻压缩包内包含一个USB调试助手，可以调试HID通信

本资源给出了bch码的编码的c语言代码，利用移位寄存器来产生校验位

Spark开发指南.pdf本书参考Spark官方文档和源码，通过本书你将精通Spark的安装、配置、开发、监控和调优。Apache SparkSpark是伯克利 APMLab实验室精心打造的,力图在算法( Algorithms)、机器( Machines)、人( People)之间通过大规模集成,来展现大数据应用旳一个平台,其核心引擎就是 Spark,其计算基础是弹性分布式数据集,也就是RDD。通过Spark, MPLab运用大数据、云计算、通信等各种源,以及各种灵活的技术方案,对海量不透明的数据进行甄別并转化为有用的信息,以供人们更好的理解世界。 Spark已经涉及到机器学习、数据挖掘、数据库、信息检索、自然语言处理和语音识别等多个领域。Sparp ecological environment陡着 spark的日趋完善, Spark以其优异的性能正逐渐成为下一个业界和学术界的开源大数据处理平台。随着 Spark1.1.0的发布和 Spark生态圈的不断扩大,可以预见在今后的一段吋间内, Spark将越来越火热。spak生态圈以Spa为核心引擎,以HDFS、S3、 Tachyon为持久层读写原生数据,以 Mesos、YARN和自身携带的Standalone作为资源管理器调度job,来完成spak应用程序的计算;而这些spak应用程序可以来源于不同的组件,如 Spark的批处理应用、 Spark Streaming的实时处理应用、 Spark sρL的即席查询、 BlinkDB的权衝查询、MLib或 MLbase的机器学习、 GraphX的图处理等等。更多的新信息请参看伯克利 APMLab实验室的项目进展htps:/ mplab. cS. berkeley. edu/projects或者 Spark峰会信息htp:/ spark-summit org。Spark Spark MLlib GraphXSQL Streaming(machine(graph)learningApache SparkSparkSpark是一个快速的通用大规模数据丛理系统,和 Hadoop MapReduce相比更好的容锆性和内存计算高速,在内存中运算100倍速度于 MapReduce易用,相同的应用程序代码量要比 MapReduce少25倍提供了丰富的AP支持互动和迭代程序Spark大数据平台之所以能日渐红火,得益于 Spark内核架构的优秀·提供了支持DAG图的分布式并行计算框架,减少多次计算之间中间结果O开销·提供 Cache机制来支持多次迭代计算或者数据共享,减少开销*·RDD之间维护了血统关系,一旦 RDD fail掉了,能通过父RDD自动重建,保证了容错性·, RDD Partition可以就近读取分布式文件系统中的数据块到各个节点内存中进行计算使用多线程池模型来减少task启动开稍shuffle过程中避免不必要的sor操作采用容错的、高可伸缩性的aka作为通讯框架SparkStreamingSparkstreaming是一个对实时数据流进行高通量、容锴处理的流式处理系统,可以对多种数据源(如Kdka、Fume、Twitter、zero和TCP套接字)进行类似map、 reduce、join、 window等复杂操作,并捋结果保存到外部文件系统、数据库或应用到实时仪表盘Sparkstreaming流式必理系统特点有捋流式计算分解成一系列短小的批处理作业将失败或者执行校慢的任务在其它节点上并行执行较强的容错能力(基于RDD继承关系 Lineage)使用和RDD一样的语义Spark SQLSpark SQL是一个即席查询系统,可以通过SQL表达式、 HiveQL或者 Scala dsl在 Spark上执行查询。Spark SQL的特点·引人了新的RDD类型 SchemaRDD,可以象传统数据库定义表一样来定义 SchemaRDD, SchemaRDD由定义了列数据类型的行对象构成。· SchemaRDD可以从RDD转换过来,也可以从 Parquet文件读入,也可以使用 Hive QL从Hve中获取·在应用程序中可以混合使用不同来源的数据,如可以将来自 HiveQL的数据和来自sQL的数据进行jn操作。·内嵌 catalys优化器对用户查询语句进行自动优化MLlibMLib是Spak实现一些常见的机器学习算法和实用程序,包括分类,回归,聚类,协同过滤,降维,以及底层GraphXGraphX是基于 Spark的图处理和图并行计算AP。 GraphX定义了一个新的概念:弹性分布式属性图,一个每个顶点和边都带有属性的定向多重图;并引人了三种核心RDD: Vertices、 Edges、 Triplets;还开放了一组基本操作(如 subgraph,joinvertices, and mapReduce Triplets),并且在不断的扩展图形算法和图形构建工具来筒化图分析工作生态圈的应用Spark生态圈以 Spark为核心、以RDD为基础,打造了一个基于内存DAG计算的大数据平台,为人们提供了一栈式的数据处理方奚。人们可以根据不同的汤景使月主要应用场景用户曲像的建立用户异常行为的发现社交网络关系洞察用户定向商品、活动推荐spak运维相关安装配置、监控等,请求参考《 Spark运维实战》graphiteum install -y bitmap bitmap-fonts-compat Django django-tagging fontconfig cairo python-devel python-memcachedpython-twisted pycairo mod python python-Idap python-simplejson memcached python-zope-interface mod wsgipython-sqlite2Spark BaseSpark开发环境Spark本身是由 scala语言开发的,提供了三种语雷接口: Scala、Java、 Python。根据自己的喜好可以使用相应语言的开发工具。本书使用 scala语言做为开发Spak应用的语,采用 Eclipse为主要的开发工具主要介绍了两个流行的开发工貝: Eclipse、 Intell IDEA。JDK安装配置下载官方网址:htp/www.oracle.com/technetwork/javaljavase/downloads/jdk7-downloads-1880260hml选择好操作系统版本,32位操作采统选择带j586的安装文件;64位操作系统选择菅×64的安装文件。Linux操作系统推荐下载 tar. gz格式的安装文件, Window当然也只有exe格式的文件。Linux下安装解压tar -zxvf jdk-7ug-linux-1586. tar. gz-C/opt/In-/opt/jdk170_09 /opt/jdk设置环境变量用ⅵ编辑配置文件:/etc/ profileexport JAVA HOME=/ pt/jdkexport CLASSPATH=$JAVA HOME/lib/dt jar: SJAVA HOME/lib/tools. jarexport PATH= $JAVA HOME/bin: s PATH保存退出按Esc然后输入Wq使配置生效source /etc/profileWindows下安装选择好操作系统版本是32还是64,解压双击进行安装一路下一步,便可安装成功。设置环境变量测试是否成功命合行输人Java -versIon如果出现下面提示说明成功

Linux+Oracle 11g+RAC+12cc+adg中国史上最详细生产系统下实施文档我保证：这是史上最详细的生产系统oracle全流程下真刀真枪实战文档。