关于四元数法捷联惯导解算算法的matlab程序组合包

最近公司需要实现 Android下（PDA）与公司设备（PLC）通讯和操作设备.(本人Android开发也是这个项目边学边做)，中间遇到了很多坑，也感谢CSDN上资源的共享。也看了不是Modbus4j.jar 实现ModbusTCP和PLC的小例子。。。总是云里雾里。现在结合项目抽取操作ＰＬＣ的代码贡献给这方便有需求的朋友。。。程序用到seroUtils.jar，modbus4J.jar。可以读写ＰＬＣ（１６位），同时也做了下浮点值的写入和处理。。朋友可以在此基础上进行变化。。。

地震处理软件SAC格式数据国际通用地震格式

进行频谱分析程序，用matlab编程实现

【实例简介】负荷预测算法 使用多种算法（线性回归，随机森林，支持向量机，BP神经网络，GRU，LSTM）进行电力系统负荷预测/电力预测。通过一个简单的例子。各种算法（线性回归，随机森林，支持向量机，BP神经网络，GRU，LSTM）用于电力系统负荷预测/电力预测。

该文件是一个基于MATLAB两电平仿真模型，经仿真验证可行，效果不错

这是一款material UI风格前端模板 ，效果请参考 http://demos.creative-tim.com/material-dashboard-pro/examples/dashboard.html.如果大家觉得5分太多，可以到这个网站上下载免费版，我这里提交的是收费的Pro版。大家可以对比下效果。

多传感器分布式Kalman 滤波融合算法

能够读取遥感影像，并利用Moravec和fostner算子提取特征点，内附影像

全志F1C200s F1C100s 中文资料，英文翻译，下载后请自觉收藏，不要再上传到其它网站上赚取积分，是我花了118大洋翻译后共享给大家使用的，请自觉遵守，如有发现将会到上传的网站上投诉上传人员

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group