PyGame官方手册（官方API）包含中文和英文（全）

竖版学术海报ppt模板。大小为A0，33.1*46.9英寸，即841mm*1189mm。共10个模板.

matlab仿真轨道角动量，模态值从0到+3，画出平面波和涡旋波的示意图

【实例简介】适合目标检测，yolov3,ssd等目标检测算法，数据集包含xml坐标信息的标签。pytorch版本下的yolov3训练实现火焰检测(https://codingchaozhang.blog.csdn.net/article/details/107167792#comments_14120984)

该程序可生成随机相位屏，用于模拟大气的随机相位，可通过调整参数，生成可视化大气图像。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

用simulink实现直流电机模型的开环仿真，再通过加控制器（比例环节和比例积分环节）实现其闭环仿真。

南京研旭的CCS3.3 28335 DSP开发例程。 例程极其丰富，应用广泛，价值很高。共计58个例程内容有GPIO、TIMER、WATCHDOG、CAP、QEP、CAN、SPI、MCBSP、I2C、AD、DA、PWM、UCOS、FFT、FIR、EEROM、RAM、FLASH、DMA、TCP等等

【实例简介】目前，世界各国都开始重视人工智能的发展。2017 年 6 月 29 日，首届世界智能大会在天津召开。中国工程院院士潘云鹤在大会主论坛作了题为“中国新一代人工智能”的主题演讲，报告中概括了世界各国在人工智能研究方面的战略：2016 年 5 月，美国白宫发表了《为人工智能的未来做好准备》；英国 2016 年 12月发布《人工智能：未来决策制定的机遇和影响》；法国在 2017 年 4 月制定了《国家人工智能战略》；德国在2017年5月颁布全国第一部自动驾驶的法律；在中国，据不完全统计，2017 年运营的人工智能公司接近 400 家，行业巨头百度、腾讯、阿里巴巴等都不断在人工智能领域发力。从数量、投资等角度来看，自然语言处理、机器人、计算机视觉成为了人工智能最为热门的三个产业方向。

用SQL数据库实现的中学排课管理系统，有需求分析，和实现的各种功能，适合用来学习做SQL Sever 的课程设计。希望能帮助到

计算机科学引论英文版，算是比较全的了，这是2017英文版的。