qt面试相关

PSAT软件及900页原版教程.rarPSAT软件 原版教程 工具加教程。

本程序适合地形起伏不大的方形方格网法土方量计算，使用前请先在matlab中建立A矩阵并标定方格点的高程，比较适合大学生解决土方量计算时的繁琐计算。属于土木工程施工问题

android 传感器使用的demo，包括光线传感器，加速度传感器，距离传感器和方向传感器。

　 对于直线永磁同步伺服电机 , 提出了一种高精度的 H ∞鲁棒位置控制器。其中, 使用H ∞鲁棒控制理论设计反馈控制器, 在具有模型摄动及外部干扰的情况下 , 保证了闭环系统的鲁棒稳定和鲁棒性能; 针对被控对象的标称模型设计 IP 积分 - 比例位置控制器 , 以满足位置系统性能要求。设计的控制器既保证了系统的鲁棒性 , 又保证了系统的跟踪性能。仿真结果表明了提出方案的合理性和有效性。

Xilinx的Virtex-7系列所有PCB及原理图封装，感谢下载。

微电网有关的经济调度文献，对于微电网各个模块有详细的叙述

基于信息非对称双方演化博弈模型的matlab程序源代码，已经运行通过的

摘要： matlab由于其强大的功能而被广泛应用于很多工程领域。在扩频通信中通常的做法是用一扩频序列与信号相乘，从而得到频谱的扩展或压缩， 因而扩频序列的性能直接决定着通信质量。伪随机序列中的 m序列和 gold序列最常用作扩频序列.

Matlab GUI做的图像边缘检测程序，分别用经典时域算子和小波多尺度分析检测图像边缘

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group