altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
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ISO 11898-3 中文
ISO 11898-3-2006道路车辆—控制器区域网络（CAN）—第三部分：低速，容错，媒体专用接口前ISO(国际标准化组织)是一个世界性的国际化标准组织(ISO成员团体)。制定国际标准的工作通常是由ISO技术委员会来完成的。何一个对已绎成立的技术委员会感兴趣的成员机构都有权派代表参加该委员会。与ISO有关的国际组织,政府和非政府国际标准化组织,也可参加有关的工作。ISO在电工技术标准化的所有事项中都与国际电T委员会(IEC)有密切的合作国际标准是根据 ISO/IEC法规、第2部分屮给出的法规进行起草的。技术委员会的主要工作为制定国际标准。经过技术委员公通过的国际标准草案都会分发给各成员团体进行投票。国际标准需要经过至少75%的各成员机构的投票审批之后才能够出版发行。文件中的一些元素可能会是属于某项专利,这一点需要引起注意。ISO没有鉴别这些专利的义务。ISO11898-3是山 ISO/TC22,道路车辆,SC3小组委员会,电器及电子设备技术委员会起草的取消第一版的ISO11898-3,并使用在技术上口经经过修订的ISO11519-2:1994将其替代ISO118%8包含以下的部分,在道路车辆的总标题之下一控制器区域网络CAN部分1:数据伡层和物理信号。部分2:高速媒体访问单元一部分3:低速,容错,媒体专川接口。一部分4:通信的时间触发部分5:低功耗模式下的高速媒体访问单元介绍ISO11898第一次发表是在1993年11月,包括控制器局域网(CAN)数据链层以及高速物理层。在对IsO11898审查和调整中:IsO11898-1描述了数据链层的协议以及媒体访问的控制ISO11898-2对高速的媒体访问单元(MAU)以及媒体专用接口(MDI)进行了规定取消ISO11898-1:2003以及ISO11898-2:2003,取代ISO11898:1993。除了高速CAN之外,最初由ISO115192所包含的低速CAN的发展,获得了诸如容错技术的新的方式。ISO11898部分的主题为对获得此窄错技术的必要条件以及容错本身的规范进行定义和描述。特別是对媒体专用接口和媒体访问控制的部分进行描述。道路车辆-控制器区域网络(CAN)部分3:低速,容错,媒体专用接口1范围此IsSO11898部分制定了在之间安装有控制器区域网终(CAN)的道路车辆的电子控制单元在40 kBit/s到125 kBit/s的传输率之间建立一个交换数字信息的特性。CAN是一个支持分布式控制和多路控制的串行逦信协议。此ISO11898部分介绍了低速CAN应用中的容错方式,以及符合 ISO/OSⅠ分层模型的物理层部分。此ISO11898部分包含以下的物理层部分:一媒体相关接口(MDⅠ)—物理媒体链接(PMA)。另外,此ISO11898部分也对物坦层部分的信号(PLS)以及媒体部分的接入控制(MAC)的定义有一定的影响。在OSI模型中的所有的其他层,既不在CAN协议之内与之匹配以及也不作为用户电平的一部分,也不会影响低速CAN物理层的容错行为,因此不能够构成此ISO11898的一部分。2术语和定义出于使用此文档的目的,使用下列术语和定义。2.1总线所有的儿点都达到了被动链接的允许在两个方向传输的通信网终的布局结构2.2总线故障由诸如屮断,短路等所引起的一个物理总线机能失常的故障。2.3总线值两个互补的逻辑值的其中的显性和隐性。注释:显性值代表一个逻辑“0”隐性值代表一个逻辑“1”。在显性和隐性位同时传输时,所导致的总线值应该为显性。2.4总线电压相对于地面的每个CAN节点的总线电路CANL和CANH的电压。注释: VCAN L和VcANⅡ表示总线电压。差分电压diffCANH和CANL线之间所能看到的电压。注释:Vd=VCAN IIVCAN L2.无故障通信不丢失信息的操作模式。2.7谷错在指定的至少有一个性能下降的总线故障条件下运行的能力。例如:减少信号的信噪比2.8收发器的循环时间延迟从施加一个逻辑信号到收发器逻辑一侧的输入口到收发器逻辑一侧的输出口检测到此信号的延时时间。2低功耗模式降低功耗的工作模式。注释:低功耗模式下不干扰其他节点之间的通信2.10节点链接到通信线路,能够根据给定的通信协议规范通过网终进行父换的组装点。2.11普通模式在网终通信中积极参与(发送和/或接收)的收发器的工作模式2.12T作电容有一个或多个节点能够检测到链接器的总线线路的总电容,受媒体的布局结构和物理介质的影响13物理层实现ECU与总线之间进行连接的电路。2.14物理介质(总线的)成对的电线,平行或双绞线,屏蔽或非屏蔽注释:单个电线,可表示为CANH和CANL。2.15接收器用其将信息转换成逻辑信息或数据信号的物理信号的转换设备2.16发射器将逻辑信息或数据信号转换为电信号,使这些信号能够通过被物理介质进行传输的设备2.17收发器适用于物理层的逻辑信号设各,反之亦然。3缩略语ACK应答CAN控制器区域网终RC循环冗余校验CSMA载波侦听多路访问DC数据长度码ECU电子控制单元EOF结束帧FCE故障本质的界定IC集成电路LAN局域网LLC逻辑链路控制LME层管理实体LPDU LLO协议数据单元SB最低有效位LSDU LLO服务数据单元LS-MAU低速媒体访问单元MAC媒体访问控制MAU媒体访问单元MDI媒体独立接口MPDU MAC协议数据单元MSB最高有效位MSDU MAC服务数据单元NRZ不会返回到零OSI开放式链接系统PL物理层PLS物理层信号PMA物埋介质附属物RTR远程传输请求SOF帧头4OSI参考模型根据在图1中所显示的OSI参考模型,CAN架构代表两层:一数据链路层;物理层。此部分对一个具有容错的低速的CAN收发器的物理层的进行了介绍。只给出了些对数据链层的影响。0SI参考模CAN架构层绍蚊据链层LLCMAC数据链物理物理层MAMDI图1OSl参考模型CAN分层架构5MD规范5.1物理媒休51.1一般说明用来对CAN散播进行传输的物理介质应为一对并行(或双绞线)的线,屏蔽或非屏蔽取决于EMC的要求。分别对线进行标记为CANH和CANL。在显性状态,CANL的电平低于隐性状态时的电平,CANH电平高于隐性状态时的电平。5.1.2总线连接节点CANH和CANL两线的终止端为一个能够被各自的节点识别的终端网络。每条线的总终端电阻应高于或等于1009。但是,由于电阻制造商的限制,指定节点的终端的电阻值不应该低于5009。代表隐性状态的CANL连接到Vc,CANI连接到CANI。图2显示了一个指定总线节点的通用连接法。RTLCAN LCAN HRIH题解a可选图2-个单一总线节点的连接在图2中,终端电阻可选。这意味着,如果适当的满足整体终端的要求,在特定的条件下并不是所有的节点都需要一个独立的终端。51.3工作电容下列规程适用于一个一般用于汽车应用的简单的连线方式。他由一对如在5.1.4中描述的布局式连接的双绞铜线构成。下列在图3和4中所示的基木模型可用于计算ROP题角a驱动器。b连线图3-总线替代电路2C.12CAN H○cANL题解:a对称轴b地线图4参考网络长度1的工作电容使用公式1来对操作电容进行计算CoP=I(C+2C12)+ n Cnode +k Cplug这里CoP工作电容;C线与地线之间的电容参照电线长度单位为米(m)C12两线(假设为对称的)之间的电容参照电线长度单位为米(m)Cmod来自总线侧的一个附加总线节点的电谷;pug一个连接插头的电容;1整个网络电缆长度;n节点的数量k插头数量例子:参考关于下述示范网络的总网络电缆长度的一个典型的操作电容的值,可有下式得出(C+2C12)=120[pF/m514介质时序所允许的最大工作电谷受到诸如下列网络固有参数的限制:一总终端电阻 rterm;布线类型和布局一通信速率一采样点的电压阀值;接地漂移,等等下面的公式提供了个计算最大允许工作电容的计算方法:
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