UML网络教学系统（UML课程设计）

最大团问题代码实现 简单易懂 适合算法学习

实现图像、影像下采样，采样方法有最邻近采样法、二次插值法、双三次卷积法。matlab实现。

软件测试报告 珍藏版。好用记得回复推荐哦目 录1. 测试概述 31.1. 编写目的 31.2. 测试范围 31.3. 参考资料 32. 测试计划执行情况 32.1. 测试类型 32.2. 测试环境与配置 42.3. 测试人员 42.4. 测试问题总结 43. 测试总结 53.1. 测试用例执行结果 53.2. 测试问题解决 73.3. 测试结果分析 84. 综合评价 84.1. 软件能力 84.2. 建议 8

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

java做的图书馆管理系统。含源代码及数据库文件。功能有图书信息查询、修改、删除、添加等操作，及借阅者信息的相应管理等。

用matlab编写的一些相关InSAR数据处理程序，值得InSAR学习或研究人员下载

完成了基于RA8875自身绘图功能的文字显示、多边形显示以及触摸屏控制等功能。本程序基于SK-M32F407开发板，LCD为RA8875驱动的800x480屏幕。由于硬件可能有所不一致，需要经过改动才能移植成功到目标板上。特别注意的是，我所用的LCD的制作者不知为何故意将R和G的信号线调反了（具体可以看LCD的原理图我有上传），故本程序的色序为BGR，而不是RA8875默认的RGB。

多尺度高斯模型的图像色彩增强Matlab代买，对于大雾天气下可以实现透雾。并且对于阴影下可以使得图像细节也变得清晰，效果挺不错，不过对于视频序列效率不足。

void USART3_IRQHandler(void) //串口数据处理{ u8 temp; //定义接受数据变量 if(USART_GetITStatus(USART3,USART_IT_RXNE)) { temp = USART_ReceiveData(USART3); if (temp==0x55)GPIO_ResetBits(GPIOC,GPIO_Pin_11); //串口收到十六进制55，输出为0

键鼠套装配对工具，操作非常简单，有开关的关闭开关，内有详细教程。没有开关的可以插入电池充当开关进行下一步操作。