粒子群优化算法代码及资料

DBeaver连接Hive的Jar包，通过Java JDBC连接Hive同样可以使用。DBeaver连接Hive的Jar包，通过Java JDBC连接Hive同样可以使用。

提取图片的不变矩特征，然后利用该特征进行图片的识别，达到我们的分类。

用FPGA生成SPWM波形可编程逻辑器件B_ Address≤m;15.0m8250sfORmsend if.elprooess(Div dk AA, BB, CC, inputIf Dn ckevent and diy ck= then DN ck为ck的分频时钟减LuiAA= 1then;AA为A相查表控制位当为”时从ROM仲中取正弦值,图4礼=0.75q

VIRES Virtual Test Drive，VTD自动驾驶仿真测试方案，自动驾驶场景仿真

韩顺平PHP教程,不可多得的PHP精品教程,从第一讲到第208讲

使用pycharm写的学生信息管理系统，使用了MySQL数据库，tkinter设计图形界面。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

1 模拟PID控制.....................................................................................................................................11.1 模拟PID控制原理......................................................................................................................12 数字PID控制..............

用于matlab仿真的光伏发电并网模型，这是经典类型，可成功运行。做光伏并网读电能质量的影响中用到的。

这是一个变速齿轮的源码感谢同学老周同志的测试与支持，他可能是除我以外第一个用户。也感谢作者李维自己的努力，和所有关心支持本软件的同志。