偏微分数值解课程设计,(有设计报告)

本资源可以实现应用madplay在linux环境下应用双向链表实现MP3播放器制作，应用进程它可以实现歌曲上下切换，停止，继续

【实例简介】电能质量扰动分析分析方法主要为傅里叶、小波变换、S变换等。 基本S变换的分析电能质量扰动的程序。含暂态的暂降和稳态的谐波两种，可稍作修改更改为其他干扰状态。

在博客中说的sift笔记配套的源码。抱歉一直没来的及上传，解压可直接用。

卷积神经网络CNN代码解析，对MATLAB-deep learning master工具箱的例子进行了说明。

东华软件-HIS系统八大册-系统设计操作说明.电子病历系统作为TrakCare医院管理系统的子系统。经历着数十家大中医院的上线使用的同时，我们就展开了电子病历新框架产品的研发工作。如今电子病历新框架产品的正式发布，必定助力一线临床医护人员病历书写工作。提高效率，创造价值。

【实例简介】用servlet+Jsp实现的北大青鸟Y2的JJS的课后项目，能正常运行，功能包括：餐品显示，购物车，订单简单处理，注册登陆。 内含数据数据库T-SQL代码

nmodbus官方例程 ，包括C#和VB.net 两种语言，包括RTU和TCP的master与slave例程，

KNN分类器实现人脸识别，数据集为ORL，40个人，每人10个图片

高铁梅《计量经济分析方法与建模Eviews应用与实例》（第二版）的数据和课件 PPT好东西。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group