微电网下垂控制仿真

包括OpenGL安装所需的所有文件，内部详细介绍了OpenGL的安装步骤，并附有一段简单的测试程序！

求根MUSIC算法，不同于谱搜索MUSIC，可以给出角度

此文档为完善后的c#.net期末课程设计，功能完善，包括数据库，下载即用。

此资源主要是51单片机控制直流马达程序，可扩展为调速电风扇的程序编写，本程序以51C语言为基础，用keilc软件编写，并通过proteus软件仿真，本资源中有直接编写好的程序和proteus仿真图，下载后可直接演示功能，此程序已经过作者多次调试，能实现调速功能，拥有高、中、低和自然风等功能，并通过数码管显示档位。

SQL语句生成器的特色支持几乎所有类型的数据库，包括小型（桌面）数据库：Fox DBF、Microsoft Execl、Text、Borland Paradox、中型数据库：Microsoft Access大型数据库：Microsoft SQL Server、Sybase、Oracle数据库的连接采取ADO方式故而使用本工具，无需安装和卸载 支持几乎所有的SQL语法：排序(Order By)条件(Where)分组(Group By)分组条件(Having)计算字段SQL查询表SQL查询子句丰富的函数表别名字段别名(包括计算字段和非计算字段)联合(Union

不错的书,邱关源的另外一本经典书,关于电路方面的经典书籍 ,可以好好看看

本代码基于IDL语言开发，以我国环境一号（HJ-1）卫星影像为例，实现了HJ-1 CCD影像的大气校正。压缩包中包括了HJ-1 CCD影像的定标系数（可以根据资源卫星应用中心发布的最新系数进行替换）和查找表。供遥感初学者参考

C2000，此处具体是TMS320F28035的数据手册大全 具体包含MCU数据手册，及MCU相关外设数据手册 包含ePWM,CLA等等，还包含有寄存器手册 压缩包内涵的pdf都有标签

在直角坐标系下进行常规潮流计算含有数据文件及数据文件说明

Matlab 官方有关于HDL coder开发的详细技术文档， HDL Coder可以把Simulink模型、MATLAB代码和Stateflow框图生成位真、周期精确、可综合的Verilog和VHDL代码，很适合用于FPGA/ASCI的快速开发，里面还有大量的例程等等ContentsHDL Code generation from MATLaBMATLAB Algorithm DesignData Types and scope1-2Supported data TUsuppyted data type1-3Scope for variables1-3Operators1-4Arithmetic operate1-4Relational operators1-4ogical Operators1-5Control flow statements1-6Vector Function Limitations related to Control1-7PersistentⅤ ariables1-8Persistent Array variables1-10Complex data Type Support1-11Declaring complex signaIs1-11Conversion Between Complex and real signals1-12Support for vectors of Complex Numb1-12ystem Objects1-14Why use System objects?1-14Predefined System Object1-14User-Defined System ob1-14Limitations of HDL Code Generation for SystemObjects1-15System object Examples for HDL Code Generation.. 1-16Predefined System Objects Supported for HDL CodeGeneration1-17Load constants from a mat-file1-18Generate Code for User-Defined System Objects1-19How To Create a User-Defined System object1-1User-Defined System object Example1-19Map Matrices to ROM1-22Fixed-Point bitwise Functions1-231-23Bitwise Functions Supported for HDl Code Generation 1-23Fixed-Point Run-Time Library functions1-29Fixed-Point function limitations1-33Model State with Persistent variables and SysteObjects1-34Bit Shifting and bit rotation1-8Bit Slicing and Bit Concatenation1-41Guidelines for Efficient hdL code1-43MATLAB Design Requirements for HDL CodeGeneration1-44What is a matlab test bench?1-45MATLAB Test Bench Requirements and bestractices1-46MATLAB Test Bench requirements1-46MATLAB Test bench best practices1-46ContentsMATLAB Best Practices and Design Patterns forHDL Code generation2Model a counter for hdl code generation2-2MATLAB Counter2-2MATLAB Code for the counter2-3Best Practices in this Example2-4Model a state machine for HDL Code Generation2-5MATLAB State machinesMATLAB Code for the Mealy State MachineMATLAB Code for the moore state machine2-7Best practic2-9Generate hardware Instances For local functions2-10MATLAB Local functions2-10MATLAB Code for mlhdlc two counters. m2-10Implement RAM USing MATLAB Code2-13Implementation of RAM2-13Implement RAM Using a Persistent Array or Systemobject Properties2-13Implement RAM Using hdl. RAM2-14For-Loop best Practices for HDL Code generation2-16MATLAB Loops2-16Monotonically Increasing Loop Counters2-16Persistent Variables in Loops2-17Persistent Arrays in Loops2-17Fixed-Point Conversion3Floating-Point to Fixed-Point Conversion3-2Fixed-Point Type Conversion and Refinement3-16Working with Generated Fixed-Point Files3-26Specify Type Proposal Options3-33Log Data for Histogram3-37Automated Fixed-Point Conversion3-40License Requirements3-40Automated Fixed-Point Conversion Capabilities3-40Code Coverage3-42Proposing Data Types3-45Locking Proposed Data Types3-47Viewing functions3-47lew1ariables3-48Istogram ...3-54Function Replacements3-56Validating Types3-57g Numerics3-57Detecting Overflows3-57Custom plot functions3-59Visualize Differences Between Floating-Point and Fixed-Point results3-61Inspecting Data Using the Simulation Data Inspector 3-67What Is the Simulation Data Inspecto3-67Import Logged Data3-67Export Logged data3-67Group signals3-67Run options3-68Create Report3-68Comparison Options3-68Enabling Plotting Using the Simulation Data Inspector 3-68Save and Load simulation Data Inspector Sessions3-68Enable Plotting Using the Simulation Data Inspector 3-70From the UI3-70From the Command Line3-70Replacing Functions Using Lookup TableApproximations·3-72Replace a custom function with a lookup Table3-73From the UI3-73i ContentsFrom the Command line3-81Replace the exp Function with a Lookup Table3-84From the ui3-84From the Command line3-92Data Type Issues in Generated Code3-94Enable the highlight Option in a MaTLAB CoderProject3-94Enable the Highlight Option at the Command Line... 3-94Stowaway doubles3-94Stowaway singles3-94Expensive Fixed-Point operations3-94Code GenerationCreate and set Up Your Project4-2Create a New Project4-2Open an Existing ProjectAdd Files to the project4-4Primary Function Input Specification4-6When to Specify Input Properties4-6Why You must Specify Input Properties4-6Properties to Specify4-6Rules for Specifying Properties of Primary Inputs4-8Methods for Defining Properties of Primary Inputs4-8Basic hdl code generation with the workflowAdvisor4-10HDL Code Generation from System Objects4-14Generate Instantiable code for functions4-19How to generate Instantiable Code for Functions4-19Generate Code Inline for Specific Functions4-19Limitations for instantiable code generation forFunctions4-19Integrate Custom HDL Code Into MATLAB Design.. 4-21Define the hdl. Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents