BLDC仿真模型

本系统是基于svm训练得到的分类器，代码包含了数据集的预处理和模型训练，对给定测试集进行测试，并根据已有标签计算准确度。代码内有详细注释，下载即可运行。如有疑问可联系

无线电导航系统

混合定位中很不错的一篇文章，看过之后很受启发在TOA和AOA误差服从零均值的高斯分布时,以上⑧无AOAQ阵中AOATOA/AOA混合定位算法的克拉美一罗下界(CRLB)为:校准离差取rP=(GQG)90Q阵中AOA校准离差取(x-x1)/其中:G=(x-x r(y-m)/r(19)洲6050(x)2(+(y-y))(x-x)(+(y-y)0.020.040.060080.100.12(x-x1)AOA标准离差(stda,单位radx-图1都市环境中算法性能比较3仿真与分析为了检验和比较算法在实际蜂窝网络信道环境中的定位性能,假定在一蜂窝网络中,小区半径为2500m,参与TOA测量的BS为服务BS和4个相邻的BS,其位置坐标分别为(0,0),(4330,2500),(4330,2500),(0,5000),(-4330,2500)。假定由测量系统造成的TOA测量误差服从均值为0,方差为30米的高斯分布,信道环境造成的NIOS误差满是TP1.5信道模型14,服务BS始终能够提供AOA,AOA测量误差服从均值为0和一定标准差的高斯分布。图1为都市环境中假定只有服务BS能视距(LOS)传播时,MS在服务小区内均匀分布,在不同AOA标准差下算法定位误差在125m内的概率。图中可见,Q矩阵中σα的取值对算法定位性能有很大影响,在AOA标准差较小时用TOA测量值η近似替代σa能取得更好的定位性能,这是由于WLS算法采用了Q阵加权。此外,120只要AOA测量值达到一定精度(标准差小于一定值),采用10-10A-A0A00TOAAOA混合定位法就能取得比单纯TOA定位更好的性能。图29080为乡村环境中在不同AOA标准差下,由单纯TOA及 TOA/AOA70定位法(Q矩阵中取n=r)得到的由均方根误差(RMSE)表示的定位性能。由图2可见,乡村环境中由于TOA测量精度较高,30对AOA的精度要求也高。只有当AOA标准差更小(小于10-3)AOA标准离差(og)时,混合定位算法才能取得比单纯TOA定位更好的性能。图2乡村环境中算法性能比较为了检验MS与服务BS距离对算法定位性能的影响,在一般都市环境中可以假定MS位于与服务BS具有不同距离的两个位置(1200,0)和(2400,0)分别进行定位估计,五个BS具有非视距TOA测量值的概率分别为:0、0.2、04、0.6、0.8、1,服务BS能够提供的AOA测量误差分别服从均值为0,标准差为01、0.0lrad的高斯分布,Q矩阵中用r近似替代σn,对每个位置在每种条件下分别进行100次测量,算法在无AOA及具有两种标准差的AOA时的定位结果(RMSE)如图3、4所示仿真结果表明:AOA参与卜AOA标准离差=001AOA标准离差=0,01定位只有在AOA本身误差不大AOA标准离差=0.1AOA标准离差=0.1无AOA无AOA的情况下,才能对定位性能有改200善;如果AOA本身误差增大150则对TOA定位结果并不会有改l00善;MS距离服务BS越近,则50采用混合定位算法的效果越好。00.00.204060.810000.20.40.608104结论BS非视距概率Bs非视距概率图3个同标准差时算法图4不同标准差时算法本文的分析和仿真结果表性能比较(1200,0)性能比较(2400,0)明,只要服务BS提供的AOA测量值达到一定精度,合理选择Q矩阵中AOA标准差取值,本文提出的 TOA/AOA混合定位算法就o1994-2012ChinaAcademicJournalElectronicPUblishingHouseAllrightsreservedhttp:/www.cnki.neto1994-2012ChinaAcademicJournalElectronicPUblishingHouseAllrightsreservedhttp:/www.cnki.net

【实例简介】文档目的：通过一个例子，详细介绍如何使用Cyclone III FPGA实现对4片DDR的控制。 包含内容： 1. 生成DDR Control IP核的过程； 2. 如何参考Altera所提供的IO管脚说明文档； 3. 如何分配DDR的数据线； 4. 如何分配DDR的地址线； 5. 如何分配DDR的控制线； 6. 在综合、布线过程中所需注意的实现细节，为提高效率如何使用的辅助工具； 本文档为原创，是结合一个实际的项目所编写的，对其它的项目实现具有较强的借鉴和指导意义。

【实例简介】深度学习和机器学习PPT作图相关素材，由dair.ai出品，详情见github地址：https://github.com/dair-ai/ml-visuals

matlab编写的BOC调制的仿真，包括信号的发生，频谱问题，BPSK的对比，信号的捕获

串口调试工具，共4个（XCOM V2.0 原子+ComMonitor单个文件版+串口 UartAssist+串口 sscom5.10a串口调试程序）

MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. The material contained herein is4 provided on an"as iS basis and to the maximum extent permitted by applicable law, this material is5 provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIP6 hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not7 limited to, any (ifany)inplied warranties, duties or conditions of merchantability, of fitness for a8 particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of9 viruses, and of lack of negligence10 All materials contained herein are protected by copyright laws, and may not be reproduced, republisheddistributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express12 prior written permission of MIPI Alliance. MIPl, MIPI Alliance and the dotted rainbow arch and all related3 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and14 cannot be used without its express prior written permission15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET16 POSSESSION. CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH17 REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT.IN NO EVENT WILLI8 ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT9 OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE20 GOODS OR SERVICES. LOST PROFITS. LOSS OF USE. LOSS OF DATA OR ANY INCIDENTAL.21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH25 DAMAGES26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance30 with the contents of this Document. The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential

有人要的完整版，不过没有字段信息。我能认出的就是行号，行别，地区代码，行名，电话，入网日期？，大概这么几类，只能大家自行去联想了。

【实例简介】这是一个学习机器人避障算法的matlab仿真代码，直接下载运行就可以使用，备注非常详细，大家可以自定义避障地图，也可以更改参数实现不同的避障