模糊PID详解及自整定

基于MFCC和SVM的说话人性别识别 建立了普通话语音性别数据库 ,提出联合梅尔频率频谱系数(Mel-frequency Cepstrum Coefficients,MFCC)的特征提取方法和支持向量机(Support Vector Machine,SVM)的分类方法进行说话人性别识别 ,并与其它分类方法进行比较 ,实验结果表明该方法的说话人性别识别准确率达到98.7%,明显优于其它分类器。

mirror driver应用程的原理。使用mirror driver加快屏幕数据获得速度。一个mirror driver的hello world例子。教程：http://blog.csdn.net/qwer430401/article/details/53047022

本代码是基于压缩感知的光谱成像代码，与杜克大学文章想匹配

文中用几种不同的去噪方法分析了一维去噪 包括小波分析 自适应滤波 以及频谱分析 功率谱分析 和滤波器的设计 并且有详细的matlab算法

该程序主要使用C#实现了KD树的构造，同时利用构造的KD树，查找距离目标点的最近邻节点，还有在此基础之上改进的BBF搜索算法，当然同时在此之上进一步改进K近邻的搜索算法

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

机械制图基础机械制图基础机械制图基础机械制图基础机械制图基础 齐全啊～～～大家快下啊～～～

多径信道下 简单OFDM matlab仿真 移动通信课程作业，瑞利3径信道

描述nsga-ii算法的文档，对nsga-ii感兴趣的有帮助

【实例简介】PCA+LDA降维，KNN分类器，实现人脸识别，数据集为ORL