测试之美（高清程序员十本必读书之一）.pdf

很简洁易懂的正弦信号发生器verilog代码，附带有modelsim仿真测试脚本文件，已用于我自己的项目中

ASP 旅游管理系统 动态网页 含课程设计

本资源是一个基于Matlab软件的D-S证据理论的源代码，其中代码有相应注释，如果对程序代码存在不懂之处可留言。欢迎大家留言交流。

基于气动力的导弹姿态控制（含MATLAB仿真），有详细的理论论述和仿真程序

采用二进搜索算法的注水算法。注水算法通常用于解决OFDM或者MIMO系统中的子信道的功率分配问题。较常用

Gabor小波提取图像纹理特征，matlab语言编写,简单实用，运行通过

贡献本人自写的unity四川麻将单机版源码，代码主要使用UGUI完成 实现了发牌切牌听牌等一系列逻辑 没有写计番功能

提供IIC接口程序 及 XYdata 读写 及 固件更新方法 最新固件

该软件是在matlab上编写的电力系统暂态稳定分析程序，当系统发生故障时检验系统的稳定性，绘制出系统的功角曲线以便观察。本程序仅对3机9节点系统进行了测试，如对其他系统需自行改进。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group