自动控制原理课件（吴麒）

【实例简介】基于OpenCV实现张正友相机标定（完整程序+棋盘图），代码可直接打开运行，附有棋盘图。如有问题可直接联系博主。

超分辨率图像处理，matlab源码，效果远远优于三次插值

用vc 实现中值滤波，是冈萨雷斯图像处理书上提到的源代码，原算法。是图像处理的入门教材

双支持向量机训练函数llap twsvm

HFSS的915MHz微带天线设计仿真微波DA|专注于微射抓硬件工程师的培www.mweda.com提供最专业的ADS、HSS培训课程指标要求。若进一步考虑引入阻抗匹配馈线对天线谐振频率的影响,根据之前已仿真的结果,将贴片辐射元长度调整为74.2mm时,天线在915MHz频段表现出最佳的性能,如图3、图4所示。图1侧边馈电矩形微带贴片天线模型Armo CaponeXY Plot 1LP LIPE-田2天线模型仿真结果1(S1)Am秀 OpinionRadiation Paten 1P unnc s以nommretrtaa图3天线模型仿真结果( Directivity)Armo CorporaonXY Plot 1LP_LhoFood Sre台 urpim upet500图4天线模型仿真结果2(S1)微波DA|专注于微射抓硬件工程师的培www.mweda.com提供最专业的ADS、HSS培训课程3结论从上述仿真结果可知,选择介电常数44厚度5mm的介质基板材料,贴片辐射元尺寸为998mm74.2mm,四分之一波长阻抗匹配变换器尺寸为47.3mm×3.7m时,天线中心谐振频率在915MHz附近,工作频率点辐射主瓣E面波瓣宽度63:=84°,H面波瓣宽度θ3s=97°,天线增益Gain=325(dB)(辐射效率η=0.5),回波损耗S1=-31.77(dB)(WSWR=1.05),阻抗匹配良好,系统带宽B4=1.5%(以S11≤-14dB标准为参考),天线主平面尺寸18.2cmx13.2cm,天线各项设计指标达到预定的工程设计要求。本文所讨论的采用软件仿真验证与优化的方式相比传统实物制作并测试的方式,极大地缩减了现代天线从设计到调整实现所需的时间和成本,在工程设计上将有着广泛的应用。[参考文献][1] Stutzman Warren L, Thiele Gary A. Antenna Theory and Design( Second Edition)[M]. Beijing POST TELECOM PRESS2006,[2] Bahl I J, Bhartia P.微带天线[M].北京:电子出版社,1984[3]谢拥军,刘莹,李磊HFSS原理与工程应用[M].北京:科学出版社,2009[4]张均,刘克诚张贤铎.微带天线理论与工程M].北京国防工业出版社,198[5]钟顺时微带天线理论与应用[M].西安:西安电子科技大学出版社,1991[6]宋旭亮矩形微带天线设计与阻抗匹配网络[D].大连:大连海事大学,2008【贵任编辑:刘长青】Simulation and Verification of 915 MHz Microstrip Antenna Design Based on HFSSWU Zhi-xiong WANG HongFujian Polytechnic of Information Technology, Fuzhou, Fujian, 350003, China)Abstract: This paper introduces the processes of engineering design and simulation verification of the rectangle microstrip patch antenna working in 915 MHz Frequency by using the computer electromagnetic simula-tion software HFSS. The authors first estimate the designing parameters through the classical transmission linetheory, and then follow the steps of modeling and simulation on the software. Finally, get best results for the de-signing by optimal adjustment, while the antenna achieves its best performance indexes in the condition givenout beforeKey words: HFSS; microstrip antenna; antenna design; electromagnetic simulation8袋R足①A皆揉本队、八年轻积累m寺注于做被。射频。研件工程师的培养微波网视频培训教程推荐微波网成立于年底,并于翌年与易迪拓培训合并,专注于微波、射频和硬件⊥程师的培养,现已发展成为国内最大的微波射频和无线通信人才培养基地先后与人民邮电出版社、电子工业出版社合作出版了多本专业图书,成功推出了多套微波射频经典培训课程和等软件的使用培训课程,广受工程技术学员的好评,帮助数万名工程师提升了专业技术能力。客户遍布中兴通讯、研通高频、埃威航电、国人通信等多家国内知名公司,以及台湾工业技术研究院、永业科技、全一电子等多家台湾地区企业。示皿中文视频培训课程套装ANSYS LIFSS国内最全面和专业的培训教程套装,包含套视频教程和本教材,李明洋老师讲解;结合最新工程案例,视频操作FSs培訓程罄裴演示,让学习不再难。购买套装更可超值赠送个月免费学习答疑,让您花最少的成本,以最快的速度自学掌握【点击浏览详情】两周学会中文视频教程李明洋主讲,视频同步操作演示,直观易学。课程从零训起,通过两周的课程学习,可以帮助您快速入门、自学掌握真正做到让学习不再难…【点击浏览详情】微波器件仿真分析实例中文视频教程进阶培训课程,中文视频,通过十个仿真设计工程应用实例,带您更深入学的实际应用,掌握高级设置和应用技巧…【点山浏览详情】天线设计入门中文视频教程是天线设计的王者,该教程全面解析了天线的基础知识天线设计流程和详细操作设置,让天线设计不再难…【点击浏览详情】雷达散射截面分析中文视频教程全面剖析了如何使用仿貞计算各种目标物体的雷达散射截面),包括:单站双站和宽频【点击浏览详情】了解详情,请查看微波网(微REDA黄沫气形队、年好验积m可m专于做被,射频,录件工程斯养微波射频测量仪器培训课程套装合集测试仪器培训课程套装搞射频微波,不会仪器操作怎么行!矢量网终分析仪、频谱仪、取+书最+提专手E示波器、信号源是微波射频工程师最常用的测量仪器。该培训套装集合了直观的视频培训教程和详尽的图书教材,旨在帮助您快速熟悉和精通矢网、频谱仪、示波器等仪器的操作…【点微波EDA员wwww.nwra.com击浏览详情】学习培训课程套装AD学习调课程套装心吧口国内最全面和权威的培训教程,详细讲解了在微波射频电路、通信系统和电磁仿真设计方面的应用。课程是山具有多年使用经验的资深专家讲解,结合工稈实例,直观易学;能计您在最短的时间内学会,并把真正应用到研发工作中去…【点击浏览详情】我们的课程优势※成立于2004年,一直专注于射频工程师的培养,行业经验丰富,更了解您的需求※视频课稈、既能达到现场培训的效果,又能免除您舟车劳顿的辛苦,学习工作两不误※经验丰富的一线资深专家主讲,结合实际工程案例,直观、实用、易学※更多实用课程,欢迎登陆我们的官方网站或者登陆我们的官方淘宝店0A|-专注于微波、射频、硬件工程师的培养,址

Xilinx FPGA最小系统原理图(XC3S400+USB2实用)

【实例简介】是一个很简单的个人博客网页，是用html写的，用到部分html5

端口扫描器程序，实现了：TCP Connect扫描TCP SYN扫描TCP FIN扫描TCP ACK扫描TCP NULL扫描TCP XMAS扫描UDP扫描

asp.net学生成绩管理系统(源代码)+毕业论文.doc.rar包含了完整的源程序代码和毕业设计论文

PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510