DDCFPGA
代码说明：
针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波. (For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T receiver machine multi-rate DDC module, and the simulation in the FPGA implementation. Numerical oscillation in the complex mixer module, based on the input signals of different bandwidths (6M/8MHz) choose a different group of complete decimation filter extracted factor 3 or 4 of the multi-rate processing tasks, using two half-band filter (HBF) cascade to complete four times decimation filter, single-stage Chennai Nyquist filter to complete three times the decimation filtering.)
文件列表：
DVB-T中多速率DDC的设计与FPGA实现.pdf
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