800 x 600 60 Hz VGA 控制器 FLEX10

Avt_S6LX9_MicroBoard_UCF_110127，有关xilinx spartan6开发板的相关参考设计。(Adding Custom IP to an Embedded System, the relevant reference on xilinx design.)

带有电网电压反馈的单相PWM整流器反馈，输出的波形很好，适合初学者学习观摩(With power grid voltage feedback single-phase PWM rectifier feedback, the output waveform is very good, suitable for beginners learning view )

用FPGA平台，5幅图片128*128的，存入rom中,按键控制停止和开始动画；

八阶巴特沃兹iir数字滤波器，四个二阶节，verilog代码实现，多路分时复用(batterworth，iir，8order，four second order section)

可综合的Verilog语法（剑桥大学，影印）.(A comprehensive Verilog Grammar (University of Cambridge, photocopy).)

thesis about design and implementation neural network using FPGA

all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

说明：  altera fpga 实现fft，用fft IP核，有matlab仿真代码(Altera FPGA implementation of FFT, FFT IP core, matlab simulation code)

说明：  Matlab to hdl code for Least_square testbench

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)