800 x 600 60 Hz VGA 控制器 FLEX10

FPGA按键加蜂鸣器实验： 加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)

SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)

说明：  本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)

4 seg display, button debouncer, and controller for parking meter

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))

A VANET research program

脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器(Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier)

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)

前段时间因项目需要编写了滑动相关运算的FPGA代码，并上板验证ok，现在发出来与大家分享

该工程描述的是一位全加器，可以用此作为基础，搭建多位全加器(The project description is a full adder can use this as a basis to build a number of full adder)