addersubtractor

给予QPSK调制的OFDM例程，简单明了的表述了OFDM的通信原理(Given OFDM QPSK modulation routine, simple expressions of OFDM communication theory)

题目来源于学校的课题系统硬件综合设计，代码中有单周期CPU设计，多周期流水线CPU设计，使用的是Verilog语言，多周期的是基于MIPS架构。

描述

802.11a的基带分组检测的verilog实现，其使用了分组检测的优化算法——延时相关保存算法，具有由于的检测性能。

自写的巴克频带滤波器组代码，生成频带滤波器组。内涵debug：输出生成的滤波器(Barker band filter bank code that generates band filter bank. Connotation debug: output generated filter)

实现基于FPGA的控制MCP2515发送的程序，本人编写通过测试，希望提供帮助(FPGA-based control program sent MCP2515, I write to pass the test, hoping to help)

DDS VHDL include everything of dds AD9914

时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)

在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)

说明：  MATLAB的SIMULINK和FPGA联合设计滤波器等，摆脱了传统的代码设计。(MATLAB's SIMULINK and FPGA jointly design filters and so on, and get rid of the traditional code design.)