Verilog LDPC码

Kluwer academic the verilog hardware description language fith edition

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

this is a Multiplier and Accumulate (MAC). written in VHDL

串口接收模块 Verilog serial port receiver module，包含bps产生模块，电平检测模块和控制模块

说明：  mojo v3 complete eagle schematic

SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)

说明：  针对XILINX 7系列FPGA 中MTG的驱动代码，代码的接口部分主要分为两个部分，一是控制DDR的DMA大小，选择读写，每次DMA的起始地址；二数据部分为AXIS。 已经在多个工程中使用。(For the driver code of MTG in XILINX 7 series FPGA, the interface part of the code is mainly divided into two parts, one is to control the DMA size of DDR, select read and write, the starting address of each DMA; the second data part is AXIS. It has been used in multiple projects.)

4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写(4-bit adder booth algorithm, the learning of computer organization help, verilog language)

first order reliability method

USB设备接口的驱动程序，采用verilogHDL语言编写，并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)