viterbi 译码 工程文件

VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6(Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6)

说明：  USB主机和设备的verilog代码，实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)

本程序主要是实现xinlinx fpga与dsp之间的双工通信(This program is to achieve duplex communication between xilinx fpga and dsp)

对数计算源程序，能够在FPGA中计算某数的对数(Determined on the basis of the source, calculated in the FPGA to a certain number of log)

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

PID算法控制点击速度，PWM脉宽调制方法(PID algorithm to control the motor Speed)

synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)

用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

以太网FPGA程序 Verilog编写以太网FPGA程序 Verilog编写啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊啊阿阿啊啊啊啊啊啊啊啊阿

rc6 algorithm designed based on verilog and is verified