viterbi 译码 工程文件

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)

说明：  使用FPGA实现sobel边缘检测的图像处理算法，更改后可直接使用在自己的系统上。(FPGA is used to implement the image processing algorithm of Sobel edge detection, which can be directly used in its own system after change.)

VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)

morris mano basic vhdl code in ise

veriog code for fodm.It includes transmitter and receiver. Transmitter part has serial in parallel out, decoder, interleaver, IFFT and finally to the transmitter block. Receiver part has the reverse order to transmitter.

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))

verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)