以太网FPGA程序

Verilog code to implment the 16 bits logic multiplier. The output is also 16bits including the document to describe the implement in detail .

说明：  adrv9009的测试平台的测试脚本，适合新人参考(Adrv9009 test platform test script, suitable for new reference)

实现按键控制AD三通道的电源转换的功能。(AD three buttons control channel to achieve power conversion)

给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)

滤波器就是对特定的频率或者特定频率以外的频率进行消除的电路，被广泛用于通信系统和信号处理系统中。(Filter is a circuit that eliminates specific frequencies or frequencies other than specific frequencies. It is widely used in communication systems and signal processing systems.)

说明：  本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。(I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book )

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)