AD_TLC549驱动程序

自编的64B/66B解码程序，做毕业设计的时候写的。(The decoding process 64B/66B , written when i am in the school。)

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

一个简单的429协议实现的VHDL语言代码，具备基本的429数据字的收发功能，并且仿真通过，效果一般。(A simple 429 protocol to realize the VHDL language code, with basic data words of 429 transceiver functions, and through simulation, the effect of general.)

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

sp605_multiboot_rdf0028_13.2_c 主要进行ICAP内部配置，在mutlboot中使用内部接口ICAP，通过state machine 控制ICAP读取 寄存器的状态值。还需要进行bit swap 对指令进行位交换

简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)

F2812串口通信,用于串口通信时使用，可以在线调整(F2812 serial communication, is used for serial communication can be adjusted online)

adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)

基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)

qsys-niosii-triple-speed-ethernet-3c120-v10-1