AD_TLC549驱动程序

实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)

1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

说明：  this code works with spi and uart interfaces.

　　本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。首先介绍了数字成型滤波的应用意义并分析了模拟和数字两种硬件实现方法，接着介绍了成形滤波器设计所需要MATLAB软件，以及利用ISE system generator在FPGA上进行滤波器实现的优势。文中给出了成形滤波函数的数学模型，讨论了几种常用成形滤波函数的传输特性以及对传输系统信号误码率的影响。然后介绍了本次设计中使用到的数字成形滤波器设计的几种FIR滤波器结构。把各种设计方案进行仿真，比较仿真结果，最后根据实际应用的情况并结合设计仿真中出现的问题进行分析，得出各种设计结构的优缺点以及适合应用的场合。(In this paper, the application of the principles and implementation of digital baseband signal pulse shaping filter is studied. First introduced the significance of digital shaping filter application and analysis of both analog and digital hardware implementation, then introduces the shaping filter design requires MATLAB software, and the use of ISE system generator on the FPGA to achieve the advantages of the filter. This paper presents a mathematical model of shaping filter function, the transmission characteristics discussed several common shaping filter functions and the impact on the error rate of the signal transmission system. Then introduced the use of this design to several digital shaping filter design FIR filter structure. The various design simulation, compare the simulation results, and finally according to the actual application and combine design simulation to analyze problems, come and where appropriate to the application advantages and disadvantages of various design s)

The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.

AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

一种计算高阶矩阵奇异值分解的FPGA实现方法。(A high-end computing matrix singular value decomposition of the FPGA realization method.)

电路四倍频算法，具有去毛刺，整形功能，方向及计数(Circuit quadruple frequency algorithm, with deburring, shaping function)

设计一个能求出一个1之间最大间隙的时序状态机。完成testbench描述，给出综合后的时序仿真结果