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Ver_I2C_eeprom
用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM,代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)
- 2013-04-10 16:14:03下载
- 积分:1
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UART 变送器
UART 变送器正以一个 8 位数据总线和 8 位地址总线。变送器 FIFO 是包含和发射机状态机包括国家: 闲着,开始的传输,传输停止的实际数据传输。UART 变送器可以连接到任何具有可配置的数据和地址总线的 UART 接收机。
- 2022-08-13 16:53:10下载
- 积分:1
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HDMI接口编解码传输模块ASIC设计_刘文杰
说明: ? 熟悉IIC协议总线协议,采用IIC总线对图像采集传感器寄存器进行配置,并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计,实现了刷新、读写等操作;为提高SDRAM 的读写带宽,均采用突发连续读写数据方式;并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分:1
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ConvolutionWithViterbiDecoding
QPSK调制下的(5,7)卷积码的编码和维特比译码与BPSK调制下(5,7)卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分:1
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CLA Verilog代码
先行进位加法器(CLA)代码的Verilog〜它包括测试平台我希望这将有助于你
- 2022-02-03 21:42:16下载
- 积分:1
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DA_Test
说明: 基于CycloneV FPGA与电阻网络的数模转换器代码,能够实现键控更改频率,通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)
- 2020-03-29 22:36:29下载
- 积分:1
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verilog_rtl
关于LDPC解码的verilog程序,包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)
- 2015-10-29 15:42:03下载
- 积分:1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分:1
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11-07-11
AD9910实现脉冲内线性调频信号,仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)
- 2013-09-16 10:52:00下载
- 积分:1
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【原创】__verilog_实现_FPGA控制_1602显示__调试笔记
FPGA控制LCD1602调试笔记 有原理介绍和源代码
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- 2022-01-25 19:22:15下载
- 积分:1