用VHDL和verilog实现的四人抢答器

Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

本书共由三篇组成。其中第一篇由第1~3章组成，介绍PCI总线的基础知识。第二篇 由第4~13章组成，介绍PCIExpress总线的相关概念。第二篇的内容以第一篇为基础。(This book comprises a total of three components. The first chapter from the first 1-3 chapters, introduces the basics of the PCI bus. Second by the first 4 to 13 chapters, introduces concepts related PCIExpress bus. The contents of the first to second basis.)

说明：  网口UDP的FPGA仿真代码，经过测试能够实现预想功能(etherneit udp verilog fpga code)

altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.

一个视频信号输入的verilog源代码，里面含有相关的使用文档。-A video signal input of the Verilog source code, which contains documents related to the use.

帧同步的VHDL程序源代码，巴克码同步实现。(Frame synchronization of the VHDL source code, Barker code synchronization)

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

基于FPGA的数字低通滤波器 。。。。。(FPGA-based digital low-pass filter。。。。。)

DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.