语言和 vhdl 文件

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......

signaltap 中文说明，内容详细。 ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)

mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过 (mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)

用FPGA实现的VGA/LCD显示的相关知识,包含了程序的主要结构和主要功能模块的实现过程-Using FPGA to achieve the VGA/LCD display relevant knowledge, including the procedures for the main structure and main function modules of the realization process

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

altera的vga示例

字长可以简单调整，即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)

CAN VHDL Code. Behavioral implementation of CAN bus interface.