液晶显示器的接口

vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)

Termometric 代码 DAC 的 14 位到 76 位 Verilog 语言。源 decoder.v 和 decoderTB.v

用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)

实现fpga上交通灯的设计，可以在开发板上实现红绿灯(Design of traffic lights on FPGA)

一个1MHz的FIR低通滤波器。 ① 时钟信号频率16MHz; ② 输入信号位宽8bits，符号速率16MHz； ③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数； ④ 写出测试仿真程序。(A 1MHz FIR low pass filter. (1) The clock signal frequency is 16MHz; (2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined. (4) Write the test simulation program.)

编辑销计划以使其更适合您的 DE2 系列主板。这是一个时钟/计时器，它使用 DE2 液晶显示当前时间。一个基于 vhdl 语言的状态机用于与液晶显示控制器进行通信。Key2 按钮重置时间。所有的 VHDL 源代码是包括在内的。

是一个LED点阵显示屏的原理图，非常详细，适合开发者学习(LED dot matrix display is a schematic diagram is very detailed, for developers to learn)

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

利用FPGA，产生三相SPWM波，与后继硬件电路配合，形成三相电源。高效，实用。(Using FPGA, produce three-phase SPWM wave, with subsequent hardware circuit with the formation of three-phase power. Efficient and practical.)

用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)