xilinx设计指南书中源代码lab2

说明：  CC217编程序，verilog实现，串行输入串行输出(CC 217 program, to achieve Verilog, serial input serial output)

说明：  用 AD9910实现的DDS 线性调频信号,调试已通过 可以使用(DDS LFM signal realized by ad9910 has passed debugging and can be used)

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)

misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

verilog数字系统设计，一本很好的verilog学习的书籍，很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)

现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)

接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code)

PCI vhdl for Fpga designer to design PCI IP

在多周期CPU的基础上设计一个前导0检测程序。(A preamble 0 detection program is designed on the basis of multi period CPU.)