基于FPGA的国密算法SM3实现

EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。 (EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.)

可逆的逻辑已收到

Verilog 写的HDMI接口源程序及说明文档(HDMI interface verilog code and specificaiton paper)

files describe how to configure an ADV7180

这是维特比译码器 verilog 代码生成器进行测试和 FPGA 验证。

基于AHB总线的sram控制器，带有memory bist(SRAM controller based on AHB bus)

CYPRESS官方给的FPGA程序，用于调试USB3.0接口(Verilog source files for debugging USB3.0 interface)

FFT源代码64。

用于ATmega128的一些通讯程序，包含I2C　UART，SPI等接口，用ICCAVR编译(for ATmega128 some communications procedures, including UART I2C, SPI interfaces with ICCAVR compiler)

约束所有时钟（包括你的设计中特有的时钟）对准确的时序分析结果而言是必不可少的。Quartus II TimeQuest Timing Analyzer为各种各样的时钟配置和典型时钟提供许多SDC命令。(Constraining all clocks, including the clocks unique to your design, is essential for accurate timing analysis results. The Quartus II TimeQuest Timing Analyzer provides many SDC commands for a variety of clock configurations and typical clocks.)