Synthesis of Majority/Minority Logic Networks

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)

本程序可以在DE1-SOC的实现10进制的FPGA数字计数器

Verilog 我认为写的非常好的细节书(Verilog In my opinion written details of the book)

FIFO is a First-In-First-Out memory queue with control logic that manages  the read and write operations, generates status flags, and provides optional  handshake signals for interfacing with the user logic. It is often used to  control the flow of data between source and destination. FIFO can be  classified as synchronous or asynchronous depending on whether same clock  or different (asynchronous) clocks control the read and write operations. In  this project the objective is to design, verify and synthesize a synchronous  FIFO using binary coded read and write pointers to address the memory  array. FFIO full and empty flags are generated and passed on to source and  destination logics, respectively, to pre-empt any overflow or underflow of  data. In this way data integrity between source and destination is maintained.  The RTL description for the FIFO is

音乐计算器的设计与实现。完成加减与或比较计算，能显示进位借位零位，能根据结果的正负发出两首不同的音乐。(Design and implementation of music calculator. Complete addition and subtraction and comparison calculation, can display carry and borrow zero, can send out two different music according to the positive and negative results.)

卷积编码器217,已验证，    conv(171,133)  x1=1+d+d^2+d^3+d^6  x2=~(1+d^2+d^3+d^5+d^6)

说明：  xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

This verilog vga test circuit

轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)

基于FPGA实现DSP与Rapid-IO网络互联()