视频运动补偿预测块的 verilog代码

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

串口自收自发测试函数，开发环境quartus12.1， 波特率只设置了9600bps，可供测试开发板串口功能。  

利用matlab，对偏振控制器进行仿真，最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)

VHDL code for MC68000

SDIO slave verilog code

时钟在单片机中的应用，用于控制中断及显示程序(Clock in the MCU application, used to control interrupt and display program)

资源描述 modelsim输出文件代码演示 verilog  内含头文件和testbench.Verilog HDL是一种硬件描述语言（HDL:Hardware Description Language），以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式。  

NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

密码锁，大学数字eda课程顺序锁的源代码，有2位或者4位的顺序锁，可以在fpga或者cpld上实现 (Password lock, digital eda course the order of the source code of the locks, the order of two or four locks, and can be implemented on the fpga or cpld)