VHDL的重要PPT资料,对初学者非常有益处

its a Fifo BASED design i also Interface DAC2904

用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)

4人抢答系统，可以计时20秒，20秒无人抢答则视作无人抢答。start之前抢答者视为违规抢答，违规抢答会警告选手。若有一人抢答则其他3人锁定，不可再抢答。aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

This free cpu-ip! use verilog

由于衍射、散射、反射和稀疏等环境损伤的增加，其后果是信号视线的丧失和干扰。自适应信号处理可以克服这些缺陷。该代码是用甚高速硬件描述语言（VHDL）编写的，用以滤除高频，减少噪声和干扰。

it is a matrix library. it is needed for fir fier.

BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)

verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用(verilog code for serial port transmit and receive code, with source code and test files, and accurate available)

作为一个简明的教程，主要宗旨是让初学者快速地了解FPGA/SOPC（可编程片上系统）开发的流程。-As a simple tutorial, the main purpose is to enable beginners to understand Express FPGA/SOPC (system on programmable chip) development process.

说明：  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)