VHDL的重要PPT资料,对初学者非常有益处

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

利用Verilog语言中的函数调用实现阶乘运算的功能(Function calls use Verilog language implementation of the factorial function computing)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

these are verilog files but i am uploading in text(notepad) format

测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)

说明：  fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

设计一个可编程间隔定时器，完成8253的功能，实现以下几点要求： 1、 含有3个独立的16位计数器，能够进行3个16位的独立计数。 2、 每一种计数器具有六种工作模式。 3、 能进行二进制/十进制减法计数。 4、 可作定时器或计数器。 -The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the timer or counter.

VHDL Programmes -2 for dumping on FPGA

DSP28335与FPGA通过spi通信，此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)

说明：  verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)