一个可编程的间隔定时器的设计，8253要完成的功能，实…

用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder

16QAM,64QAM,256QAM调制下的球形译码(16QAM, 64QAM, 256QAM modulation sphere decoding)

说明：  基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)

modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)

说明：  利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.