-
组合有限元
书中的源代码,用于颗粒材料的仿真计算。- The book" s source code for the simulation of granular materials.
- 2022-04-28 02:31:26下载
- 积分:1
-
Search algorithm search algorithm search algorithm search algorithm search algor...
搜索算法搜索算法搜索算法搜索算法搜索算法
- 2022-08-13 14:04:26下载
- 积分:1
-
java极限编程书籍,自己是才鸟,不懂穿上来和大家一起研究
java极限编程书籍,自己是才鸟,不懂穿上来和大家一起研究
- 2022-01-25 15:52:05下载
- 积分:1
-
用struts做的一个猜大小的小游戏,麻雀虽小,但五脏俱全
用struts做的一个猜大小的小游戏,麻雀虽小,但五脏俱全-This is a guess big or small games
- 2022-11-10 13:30:03下载
- 积分:1
-
eclipse从入门到精通的pdf电子书,提供出来与大家分享~!
eclipse从入门到精通的pdf电子书,提供出来与大家分享~!-eclipse from the portal to become fluent in pdf e-books, and provide up to share with you ~!
- 2022-04-14 21:40:48下载
- 积分:1
-
ejb的使用指南,我见过的最好的EJB书籍之一,希望能得到大家的喜爱...
ejb的使用指南,我见过的最好的EJB书籍之一,希望能得到大家的喜爱-the use of the guidelines, I have seen the best EJB books, we hope to be the favorite
- 2023-07-13 01:05:03下载
- 积分:1
-
Thinking in C++
语言:
English
格式:
word
Thinking in C++
语言:
English
格式:
word-Thinking in C language : English formats : word
- 2022-05-27 22:01:51下载
- 积分:1
-
Microsoft VC++ is a development IDE (integrated development environment), in oth...
VC++是微软公司开发的一个IDE(集成开发环境),换句话说,就是使用c++的一个开发平台.有些软件就是这个编出来的-Microsoft VC++ is a development IDE (integrated development environment), in other words, is to use a c++ development platform. Some software is made by the
- 2022-01-22 11:09:35下载
- 积分:1
-
FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
-
著名的矩阵算法代码,这是我们在写论文时搜集整理的。
著名的矩阵算法代码,这是我们在写论文时搜集整理的。-famous matrix algorithm code, which is the collection of papers written finishing.
- 2022-02-28 10:15:52下载
- 积分:1