sdram verilog

说明：  多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

本代码是同步FIFO的VERILOG HDL代码，代码除了实现基本的同步FIFO相同时钟域数据传输以外，代码简单易读，可以作为笔试或者面试手写代码的备考代码，作者参加大恒FPGA开发工程师岗位面试手写的同步FIFO程序就是出自本代码

用于实现锁相光子计数技术的累加器，verilog语言(Accumulator achieve specific cases for accumulator lock detection of photon counting technique)

安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计(Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

数字钟：实验中用到的小程序，用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)

说明：  LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)

OFDM中的16QAM星座映射的实现实现详细代码(In OFDM 16QAM constellation mapping to achieve the realization detailed code)

实验内容1：利用case语句完成3-8线译码器的设计，并在Quartus Ⅱ中输入。 实验内容2：参照实验一完成3-8线译码器的Testbench文件的编写，并在Quartus Ⅱ中输入。 实验内容3：在Quartus Ⅱ中调用Modelsim完成仿真，得到仿真波形。